diff mbox

[03/14] target-ppc: use separate indices for various translation modes

Message ID 54194BF9.7010102@redhat.com
State New
Headers show

Commit Message

Paolo Bonzini Sept. 17, 2014, 8:53 a.m. UTC 
Il 17/09/2014 08:22, Paolo Bonzini ha scritto:
> 
>> What if instead of having a "mmu_index" for the mmu arrays, we have a pointer
>> to the "mmu context".  This does imply an extra memory load on the fast path,
>> but probably not an extra instruction.
>>
>> With this, we can suddenly afford to have a relatively large number of mmu
>> contexts, with which we could implement address space numbers for relevant
>> targets.
>>
>> It is, of course, a much larger change, but perhaps it's of larger benefit.
> 
> Sounds good.  I can give it a shot---in the meanwhile, since I forgot to
> Cc qemu-ppc, Alex can you review/apply patch 1?

Much simpler: let's cut the size of the TLB in half on affected targets.

This does sacrifice some speed, but you still get about two thirds of
the improvement (boot speed of a Debian installation ISO: 30s without
patches, 24s with small TLB, 22s with large TLB) compared to the current
TCG target.

For 32-bit target and 32-bit host we can still use the full TLB size.

The following can be easily squashed in patch 2:


Tom, can you test this on PPC?

Paolo

Comments

Richard Henderson Sept. 17, 2014, 3:33 p.m. UTC | #1 
On 09/17/2014 01:53 AM, Paolo Bonzini wrote:
> +/* All the TLBs together must be smaller than 64k on RISC machines  */
> +#if !defined(__i386__) && !defined(__x86_64__) && !defined(__aarch64__) \
> +    && !defined(__sparc__) && !defined(CONFIG_TCG_INTERPRETER)
> +#define CPU_TLB_BITS (NB_MMU_MODES < 8 ? 8 : 12 - CPU_TLB_ENTRY_BITS)
> +#else
> +#define CPU_TLB_BITS 8
> +#endif

Hum.  Well, it's not that all the tlbs together that must be less than 64k,
it's the addend of the first entry of the last tlb that must be within 64k of
the start of env.  Nit picking, but perhaps we can word the comment better.

And if we choose to do something like this, this is where I'd prefer a define
in the relevant tcg-target.h.  Because you've missed ia64 and s390 that have
positive offsets larger than 64k (21 and 19 bits, respectively).

But otherwise I'm ok with this as a solution.


r~
Paolo Bonzini Sept. 17, 2014, 3:50 p.m. UTC | #2 
Il 17/09/2014 17:33, Richard Henderson ha scritto:
> Hum.  Well, it's not that all the tlbs together that must be less than 64k,
> it's the addend of the first entry of the last tlb that must be within 64k of
> the start of env.  Nit picking, but perhaps we can word the comment better.

Indeed.

> And if we choose to do something like this, this is where I'd prefer a define
> in the relevant tcg-target.h.  Because you've missed ia64 and s390 that have
> positive offsets larger than 64k (21 and 19 bits, respectively).

Right, but with 16 MMU modes the maximum size is 128k, well within s390
and ia64's limits.

> But otherwise I'm ok with this as a solution.

Thanks!

Paolo
Richard Henderson Sept. 17, 2014, 3:55 p.m. UTC | #3 
On 09/17/2014 08:50 AM, Paolo Bonzini wrote:
>> > And if we choose to do something like this, this is where I'd prefer a define
>> > in the relevant tcg-target.h.  Because you've missed ia64 and s390 that have
>> > positive offsets larger than 64k (21 and 19 bits, respectively).
> Right, but with 16 MMU modes the maximum size is 128k, well within s390
> and ia64's limits.
> 
My point exactly -- they weren't listed in your set of !defined conditionals,
so they'd use the reduced tlb size.


r~
diff mbox

Patch

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 0ca6f0b..ed78884 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -69,8 +69,6 @@  typedef uint64_t target_ulong;
 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
 
 #if !defined(CONFIG_USER_ONLY)
-#define CPU_TLB_BITS 8
-#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
 /* use a fully associative victim tlb of 8 entries */
 #define CPU_VTLB_SIZE 8
 
@@ -80,6 +78,16 @@  typedef uint64_t target_ulong;
 #define CPU_TLB_ENTRY_BITS 5
 #endif
 
+/* All the TLBs together must be smaller than 64k on RISC machines  */
+#if !defined(__i386__) && !defined(__x86_64__) && !defined(__aarch64__) \
+    && !defined(__sparc__) && !defined(CONFIG_TCG_INTERPRETER)
+#define CPU_TLB_BITS (NB_MMU_MODES < 8 ? 8 : 12 - CPU_TLB_ENTRY_BITS)
+#else
+#define CPU_TLB_BITS 8
+#endif
+
+#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
+
 typedef struct CPUTLBEntry {
     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not