From patchwork Wed Sep 17 08:53:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 390333 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id F173F140111 for ; Wed, 17 Sep 2014 18:54:02 +1000 (EST) Received: from localhost ([::1]:42935 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUAzt-0005MS-Ky for incoming@patchwork.ozlabs.org; Wed, 17 Sep 2014 04:53:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50504) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUAzT-00054n-Hg for qemu-devel@nongnu.org; Wed, 17 Sep 2014 04:53:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XUAzK-0002jI-GY for qemu-devel@nongnu.org; Wed, 17 Sep 2014 04:53:31 -0400 Received: from mail-wg0-x22a.google.com ([2a00:1450:400c:c00::22a]:46399) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUAzK-0002iX-8v; Wed, 17 Sep 2014 04:53:22 -0400 Received: by mail-wg0-f42.google.com with SMTP id x12so1028033wgg.1 for ; Wed, 17 Sep 2014 01:53:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=3AGKDBuvMsFijRrRJn5tB6xB10KKfwHi90uyV3C5Qds=; b=Ly48sz/XcBSwOsd+HGDXQzA7cb4uei9TbkkBLIOyEKJzBBZGHQpJBKZr+wzkQbJNc4 MoAhHGswWide8wiKCbbFrqF3PAtBt4thoGmKd6h2hG/b2HcMbqf+ZzloTfCFr3d1+ncI VnczzEWGCdU3pXEIEWDNwVmHIG0K90WVruMpwFHvHwHoXKYcrDyU34k8cBs4p4roOFjx GE4YNdwsYW1Dk51CoRWBQ2ZLd0WC623nfGQ3eBW1Dwt7orfc0xt0mPdfape6WvXqdcL9 lniF6v9B0FMvgfroo6sC2WY+kL1QmS3kjFuv1a/MqCKePuCIuH9zKGpoS5+O5LtPrWjI gjWA== X-Received: by 10.194.77.195 with SMTP id u3mr1660863wjw.115.1410943998039; Wed, 17 Sep 2014 01:53:18 -0700 (PDT) Received: from yakj.usersys.redhat.com (net-37-116-212-135.cust.vodafonedsl.it. [37.116.212.135]) by mx.google.com with ESMTPSA id dc9sm4807917wib.5.2014.09.17.01.53.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Sep 2014 01:53:17 -0700 (PDT) Message-ID: <54194BF9.7010102@redhat.com> Date: Wed, 17 Sep 2014 10:53:13 +0200 From: Paolo Bonzini User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.0 MIME-Version: 1.0 To: Richard Henderson References: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> <1410793421-6453-4-git-send-email-pbonzini@redhat.com> <5418716A.9080508@gmail.com> <54187B3D.8000909@twiddle.net> <5418810E.3080100@redhat.com> <5418846E.8070608@twiddle.net> <5418B877.8080308@twiddle.net> <1959651544.50247750.1410934939759.JavaMail.zimbra@redhat.com> In-Reply-To: <1959651544.50247750.1410934939759.JavaMail.zimbra@redhat.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c00::22a Cc: Peter Maydell , Tom Musta , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Subject: Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Il 17/09/2014 08:22, Paolo Bonzini ha scritto: > >> What if instead of having a "mmu_index" for the mmu arrays, we have a pointer >> to the "mmu context". This does imply an extra memory load on the fast path, >> but probably not an extra instruction. >> >> With this, we can suddenly afford to have a relatively large number of mmu >> contexts, with which we could implement address space numbers for relevant >> targets. >> >> It is, of course, a much larger change, but perhaps it's of larger benefit. > > Sounds good. I can give it a shot---in the meanwhile, since I forgot to > Cc qemu-ppc, Alex can you review/apply patch 1? Much simpler: let's cut the size of the TLB in half on affected targets. This does sacrifice some speed, but you still get about two thirds of the improvement (boot speed of a Debian installation ISO: 30s without patches, 24s with small TLB, 22s with large TLB) compared to the current TCG target. For 32-bit target and 32-bit host we can still use the full TLB size. The following can be easily squashed in patch 2: Tom, can you test this on PPC? Paolo diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0ca6f0b..ed78884 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -69,8 +69,6 @@ typedef uint64_t target_ulong; #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) #if !defined(CONFIG_USER_ONLY) -#define CPU_TLB_BITS 8 -#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 @@ -80,6 +78,16 @@ typedef uint64_t target_ulong; #define CPU_TLB_ENTRY_BITS 5 #endif +/* All the TLBs together must be smaller than 64k on RISC machines */ +#if !defined(__i386__) && !defined(__x86_64__) && !defined(__aarch64__) \ + && !defined(__sparc__) && !defined(CONFIG_TCG_INTERPRETER) +#define CPU_TLB_BITS (NB_MMU_MODES < 8 ? 8 : 12 - CPU_TLB_ENTRY_BITS) +#else +#define CPU_TLB_BITS 8 +#endif + +#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) + typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not