| Message ID | 1408637529-31170-1-git-send-email-fabio.estevam@freescale.com |
|---|---|
| State | Superseded |
| Delegated to: | Stefano Babic |
| Headers | show |
On Thursday, August 21, 2014 at 06:12:08 PM, Fabio Estevam wrote: > mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. > Other SoCs work with the standard 32 bytes alignment. > > Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, > which addresses the needs from mx6solox and also works for the other SoCs. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > Changes since v2: > - Use 64 bit alignment which covers mx6solox and the other SoCs as > suggested by Stefan Roese > > drivers/net/fec_mxc.c | 14 +++++++++++--- > 1 file changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c > index 4cefda4..56178d4 100644 > --- a/drivers/net/fec_mxc.c > +++ b/drivers/net/fec_mxc.c > @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR; > */ > #define FEC_XFER_TIMEOUT 5000 > > +/* > + * The standard 32 DMA alignment does not work on mx6solox, which requires > + * 64 alignment in the DMA RX FEC buffer. Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't there something completely else broken on MX6SX ? [...] Best regards, Marek Vasut
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cefda4..56178d4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000 +/* + * The standard 32 DMA alignment does not work on mx6solox, which requires + * 64 alignment in the DMA RX FEC buffer. + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also + * satisfies the alignment on other SoCs (32) + */ +#define FEC_DMA_RX_MINALIGN 64 + #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@ -286,7 +294,7 @@ static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) * Reload the RX descriptors with default values and wipe * the RX buffers. */ - size = roundup(dsize, ARCH_DMA_MINALIGN); + size = roundup(dsize, FEC_DMA_RX_MINALIGN); for (i = 0; i < count; i++) { data = (uint8_t *)fec->rbd_base[i].data_pointer; memset(data, 0, dsize); @@ -881,9 +889,9 @@ static int fec_alloc_descs(struct fec_priv *fec) /* Allocate RX buffers. */ /* Maximum RX buffer size. */ - size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN); + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); for (i = 0; i < FEC_RBD_NUM; i++) { - data = memalign(ARCH_DMA_MINALIGN, size); + data = memalign(FEC_DMA_RX_MINALIGN, size); if (!data) { printf("%s: error allocating rxbuf %d\n", __func__, i); goto err_ring;
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- Changes since v2: - Use 64 bit alignment which covers mx6solox and the other SoCs as suggested by Stefan Roese drivers/net/fec_mxc.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-)