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[U-Boot,14/23] ARM: tegra: Enable XUSB pad controller on Jetson TK1

Message ID 1408346196-30419-15-git-send-email-thierry.reding@gmail.com
State Superseded
Delegated to: Tom Warren
Headers show

Commit Message

Thierry Reding Aug. 18, 2014, 7:16 a.m. UTC 
From: Thierry Reding <treding@nvidia.com>

Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm/dts/tegra124-jetson-tk1.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Stephen Warren Aug. 20, 2014, 6:34 p.m. UTC | #1 
On 08/18/2014 01:16 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
> so that the XUSB pad controller can be appropriately configured.

Aside from the differing #address-cells at the top-level of the DT, this 
matches what's been proposed for the Linux kernel, so,

Acked-by: Stephen Warren <swarren@nvidia.com>
diff mbox

Patch

diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
index 464287e03ecf..f61736f0ef0f 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -66,6 +66,32 @@ 
 		spi-max-frequency = <25000000>;
 	};
 
+	padctl@7009f000 {
+		pinctrl-0 = <&padctl_default>;
+		pinctrl-names = "default";
+
+		padctl_default: pinmux {
+			usb3 {
+				nvidia,lanes = "pcie-0", "pcie-1";
+				nvidia,function = "usb3";
+				nvidia,iddq = <0>;
+			};
+
+			pcie {
+				nvidia,lanes = "pcie-2", "pcie-3",
+					       "pcie-4";
+				nvidia,function = "pcie";
+				nvidia,iddq = <0>;
+			};
+
+			sata {
+				nvidia,lanes = "sata-0";
+				nvidia,function = "sata";
+				nvidia,iddq = <0>;
+			};
+		};
+	};
+
 	sdhci@700b0400 {
 		status = "okay";
 		cd-gpios = <&gpio 170 1>; /* gpio PV2 */