| Message ID | 1406217175-30267-3-git-send-email-alex.bennee@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 24 July 2014 16:52, Alex Bennée <alex.bennee@linaro.org> wrote: > +/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions > + * Page D4-1736 (DDI0487A.b) "For TLB maintenance instructions that > + * take an address, the maintenance of VA[63:56] is interpreted as > + * being the same as the maintenance of VA[55]" > + */ I'd rather we didn't quote this bit of the ARM ARM, because it's obviously mangled (I'm pretty sure it should say "the value of VA[..]"). Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
Peter Maydell writes: > On 24 July 2014 16:52, Alex Bennée <alex.bennee@linaro.org> wrote: >> +/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions >> + * Page D4-1736 (DDI0487A.b) "For TLB maintenance instructions that >> + * take an address, the maintenance of VA[63:56] is interpreted as >> + * being the same as the maintenance of VA[55]" >> + */ > > I'd rather we didn't quote this bit of the ARM ARM, because it's > obviously mangled (I'm pretty sure it should say "the value of > VA[..]"). Is it OK to still reference the ARM ARM because otherwise the sign extension would look a little weird without context (although obviously we have a commit message to say we fixed something). > > Otherwise > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > thanks > -- PMM
diff --git a/target-arm/helper.c b/target-arm/helper.c index aa5d267..b0d0411 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1766,12 +1766,19 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, return CP_ACCESS_OK; } +/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions + * Page D4-1736 (DDI0487A.b) "For TLB maintenance instructions that + * take an address, the maintenance of VA[63:56] is interpreted as + * being the same as the maintenance of VA[55]" + */ + static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by VA (AArch64 version) */ ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t pageaddr = value << 12; + uint64_t pageaddr = sextract64(value << 12, 0, 56); + tlb_flush_page(CPU(cpu), pageaddr); } @@ -1780,7 +1787,8 @@ static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, { /* Invalidate by VA, all ASIDs (AArch64 version) */ ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t pageaddr = value << 12; + uint64_t pageaddr = sextract64(value << 12, 0, 56); + tlb_flush_page(CPU(cpu), pageaddr); }
According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>