diff mbox

[U-Boot] enabling ecc on P2041 and QoreIQ familly not valid for memory >= 4GB

Message ID 53C91D25.3030204@kontron.com
State Not Applicable
Delegated to: York Sun
Headers show

Commit Message

Benoit Sansoni July 18, 2014, 1:11 p.m. UTC 
Hi ,

I found out an issue when enabling ECC for P2041 platform with an amount
of memory of 8GB.
The routine "void dma_meminit(uint val, uint size)" is not adapted to
manage memory size greater or equal to 4GB due to the 'uint' type.
With this typing the dma_meminit sees 0 as size when memory is for
example at 8GB. So the ECC part of the memory is not initialized and
when going in memory the code crash.
To correct it you need to use phys_size_t type instead of uint.
It is the same thing for all routines that are called by "dma_meminit".
I attached a patch that able to correct it easily.
This patch should be integrated in the main branch I think so.

Regards,
Benoit

Comments

York Sun July 22, 2014, 10:53 p.m. UTC | #1 
On 07/18/2014 06:11 AM, Benoit Sansoni wrote:
> Hi ,
> 
> I found out an issue when enabling ECC for P2041 platform with an amount
> of memory of 8GB.
> The routine "void dma_meminit(uint val, uint size)" is not adapted to
> manage memory size greater or equal to 4GB due to the 'uint' type.
> With this typing the dma_meminit sees 0 as size when memory is for
> example at 8GB. So the ECC part of the memory is not initialized and
> when going in memory the code crash.
> To correct it you need to use phys_size_t type instead of uint.
> It is the same thing for all routines that are called by "dma_meminit".
> I attached a patch that able to correct it easily.
> This patch should be integrated in the main branch I think so.
> 
> Regards,
> Benoit
> 

This is a valid concern. Some code started when we had far less memory. We need
to comb through the code to fix more of them.

York
Benoit Sansoni July 23, 2014, 7:21 a.m. UTC | #2 
Hi York,

That what I saw in the code.

Also to test it you need to have the hardware, but the evaluation board 
P2041rdb for example does not have some ECC signals rooted for DIMM slot.
I validated the patch that I sent on a board based on P2041 with 8GB of 
memory. Obviously it works with 2GB and 4GB.

If you need help, you are welcome.

Thanks for your help
Benoit

On 07/23/2014 12:53 AM, York Sun wrote:
> On 07/18/2014 06:11 AM, Benoit Sansoni wrote:
>> Hi ,
>>
>> I found out an issue when enabling ECC for P2041 platform with an amount
>> of memory of 8GB.
>> The routine "void dma_meminit(uint val, uint size)" is not adapted to
>> manage memory size greater or equal to 4GB due to the 'uint' type.
>> With this typing the dma_meminit sees 0 as size when memory is for
>> example at 8GB. So the ECC part of the memory is not initialized and
>> when going in memory the code crash.
>> To correct it you need to use phys_size_t type instead of uint.
>> It is the same thing for all routines that are called by "dma_meminit".
>> I attached a patch that able to correct it easily.
>> This patch should be integrated in the main branch I think so.
>>
>> Regards,
>> Benoit
>>
> This is a valid concern. Some code started when we had far less memory. We need
> to comb through the code to fix more of them.
>
> York
>
>
York Sun July 23, 2014, 4:32 p.m. UTC | #3 
Benoit,

If your interest is in initializing DDR for ECC, you don't have use
dma_meminit(). There is a better and faster way to do so. All Freescale modern
DDR controllers support this feature. All you have to do is to define these macros

CONFIG_DDR_ECC
CONFIG_ECC_INIT_VIA_DDRCONTROLLER
CONFIG_MEM_INIT_VALUE

There are plenty of example for you to follow.

But again, we should fix the DMA function anyway.

York


On 07/23/2014 12:21 AM, Benoit Sansoni wrote:
> Hi York,
> 
> That what I saw in the code.
> 
> Also to test it you need to have the hardware, but the evaluation board 
> P2041rdb for example does not have some ECC signals rooted for DIMM slot.
> I validated the patch that I sent on a board based on P2041 with 8GB of 
> memory. Obviously it works with 2GB and 4GB.
> 
> If you need help, you are welcome.
> 
> Thanks for your help
> Benoit
> 
> On 07/23/2014 12:53 AM, York Sun wrote:
>> On 07/18/2014 06:11 AM, Benoit Sansoni wrote:
>>> Hi ,
>>>
>>> I found out an issue when enabling ECC for P2041 platform with an amount
>>> of memory of 8GB.
>>> The routine "void dma_meminit(uint val, uint size)" is not adapted to
>>> manage memory size greater or equal to 4GB due to the 'uint' type.
>>> With this typing the dma_meminit sees 0 as size when memory is for
>>> example at 8GB. So the ECC part of the memory is not initialized and
>>> when going in memory the code crash.
>>> To correct it you need to use phys_size_t type instead of uint.
>>> It is the same thing for all routines that are called by "dma_meminit".
>>> I attached a patch that able to correct it easily.
>>> This patch should be integrated in the main branch I think so.
>>>
>>> Regards,
>>> Benoit
>>>
>> This is a valid concern. Some code started when we had far less memory. We need
>> to comb through the code to fix more of them.
>>
>> York
>>
>>
> 
>
Benoit Sansoni July 24, 2014, 6:56 a.m. UTC | #4 
York,

I am going to check out the method that you talk about.
For now the fix allow me to boot our board with 8GB it is a good step 
for me.

Thanks
Benoit

On 07/23/2014 06:32 PM, York Sun wrote:
> Benoit,
>
> If your interest is in initializing DDR for ECC, you don't have use
> dma_meminit(). There is a better and faster way to do so. All Freescale modern
> DDR controllers support this feature. All you have to do is to define these macros
>
> CONFIG_DDR_ECC
> CONFIG_ECC_INIT_VIA_DDRCONTROLLER
> CONFIG_MEM_INIT_VALUE
>
> There are plenty of example for you to follow.
>
> But again, we should fix the DMA function anyway.
>
> York
>
>
> On 07/23/2014 12:21 AM, Benoit Sansoni wrote:
>> Hi York,
>>
>> That what I saw in the code.
>>
>> Also to test it you need to have the hardware, but the evaluation board
>> P2041rdb for example does not have some ECC signals rooted for DIMM slot.
>> I validated the patch that I sent on a board based on P2041 with 8GB of
>> memory. Obviously it works with 2GB and 4GB.
>>
>> If you need help, you are welcome.
>>
>> Thanks for your help
>> Benoit
>>
>> On 07/23/2014 12:53 AM, York Sun wrote:
>>> On 07/18/2014 06:11 AM, Benoit Sansoni wrote:
>>>> Hi ,
>>>>
>>>> I found out an issue when enabling ECC for P2041 platform with an amount
>>>> of memory of 8GB.
>>>> The routine "void dma_meminit(uint val, uint size)" is not adapted to
>>>> manage memory size greater or equal to 4GB due to the 'uint' type.
>>>> With this typing the dma_meminit sees 0 as size when memory is for
>>>> example at 8GB. So the ECC part of the memory is not initialized and
>>>> when going in memory the code crash.
>>>> To correct it you need to use phys_size_t type instead of uint.
>>>> It is the same thing for all routines that are called by "dma_meminit".
>>>> I attached a patch that able to correct it easily.
>>>> This patch should be integrated in the main branch I think so.
>>>>
>>>> Regards,
>>>> Benoit
>>>>
>>> This is a valid concern. Some code started when we had far less memory. We need
>>> to comb through the code to fix more of them.
>>>
>>> York
>>>
>>>
>>
> .
>
York Sun Aug. 12, 2014, 6:07 p.m. UTC | #5 
On 07/23/2014 11:56 PM, Benoit Sansoni wrote:
> York,
> 
> I am going to check out the method that you talk about.
> For now the fix allow me to boot our board with 8GB it is a good step 
> for me.
> 
> Thanks
> Benoit
> 
> On 07/23/2014 06:32 PM, York Sun wrote:
>> Benoit,
>>
>> If your interest is in initializing DDR for ECC, you don't have use
>> dma_meminit(). There is a better and faster way to do so. All Freescale modern
>> DDR controllers support this feature. All you have to do is to define these macros
>>
>> CONFIG_DDR_ECC
>> CONFIG_ECC_INIT_VIA_DDRCONTROLLER
>> CONFIG_MEM_INIT_VALUE
>>
>> There are plenty of example for you to follow.
>>
>> But again, we should fix the DMA function anyway.
>>

Benoit,

Have you tried my suggestion?

York
Benoit Sansoni Aug. 25, 2014, 12:35 p.m. UTC | #6 
Hi York,

Sorry for the delay. I was in holidays. I am back at work today.
Yes I have tried the other method that you proposed.
It works perfectly and It seems that this method initialized the ECC in 
a faster manner.

I faced a stability issue during ddr initialization. To resolve it I 
deactivate the autocalibration as recommended in the erratum num A-003474.
So for me the u-boot release that I am currently using is u-boot-2012.10 
and in the file u-boot-2012.10/arch/powerpc/cpu/mpc85xx/ddr-gen3.c I 
modified it
depending my ddr ram timing :

     out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
     out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
     out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
     /*dataT = fsl_dbg_timing();*/
     dataT = 0x9;
     out_be32(&ddr->timing_cfg_2, (regs->timing_cfg_2 & 0xf07fffff) | 
(dataT<<23));
     out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
     out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
     out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
     out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
     out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
     out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
     out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
     out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
     out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
     out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
     out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
     out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
     out_be32(&ddr->init_addr, regs->ddr_init_addr);
     out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);

So for me the timing_cfg_2 must be set at a deterministic value to avoid 
stability issue when the CONFIG_SYS_FSL_ERRATUM_DDR_A003474 flag is set.

Many thanks
Benoit


On 08/12/2014 08:07 PM, York Sun wrote:
> On 07/23/2014 11:56 PM, Benoit Sansoni wrote:
>> York,
>>
>> I am going to check out the method that you talk about.
>> For now the fix allow me to boot our board with 8GB it is a good step
>> for me.
>>
>> Thanks
>> Benoit
>>
>> On 07/23/2014 06:32 PM, York Sun wrote:
>>> Benoit,
>>>
>>> If your interest is in initializing DDR for ECC, you don't have use
>>> dma_meminit(). There is a better and faster way to do so. All Freescale modern
>>> DDR controllers support this feature. All you have to do is to define these macros
>>>
>>> CONFIG_DDR_ECC
>>> CONFIG_ECC_INIT_VIA_DDRCONTROLLER
>>> CONFIG_MEM_INIT_VALUE
>>>
>>> There are plenty of example for you to follow.
>>>
>>> But again, we should fix the DMA function anyway.
>>>
> Benoit,
>
> Have you tried my suggestion?
>
> York
>
>
>
York Sun Sept. 22, 2014, 5:13 p.m. UTC | #7 
Benoit,

Since you should and you have used the suggested method to initialize ECC, I am
going to close this patch as N/A. I will find some time to clean up the size
variable.

I will follow up with you on the other thread regarding dcache issue.

York


On 08/25/2014 05:35 AM, Benoit Sansoni wrote:
> Hi York,
> 
> Sorry for the delay. I was in holidays. I am back at work today.
> Yes I have tried the other method that you proposed.
> It works perfectly and It seems that this method initialized the ECC in 
> a faster manner.
> 
> I faced a stability issue during ddr initialization. To resolve it I 
> deactivate the autocalibration as recommended in the erratum num A-003474.
> So for me the u-boot release that I am currently using is u-boot-2012.10 
> and in the file u-boot-2012.10/arch/powerpc/cpu/mpc85xx/ddr-gen3.c I 
> modified it
> depending my ddr ram timing :
> 
>      out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
>      out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
>      out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
>      /*dataT = fsl_dbg_timing();*/
>      dataT = 0x9;
>      out_be32(&ddr->timing_cfg_2, (regs->timing_cfg_2 & 0xf07fffff) | 
> (dataT<<23));
>      out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
>      out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
>      out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
>      out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
>      out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
>      out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
>      out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
>      out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
>      out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
>      out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
>      out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
>      out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
>      out_be32(&ddr->init_addr, regs->ddr_init_addr);
>      out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
> 
> So for me the timing_cfg_2 must be set at a deterministic value to avoid 
> stability issue when the CONFIG_SYS_FSL_ERRATUM_DDR_A003474 flag is set.
> 
> Many thanks
> Benoit
> 
> 
> On 08/12/2014 08:07 PM, York Sun wrote:
>> On 07/23/2014 11:56 PM, Benoit Sansoni wrote:
>>> York,
>>>
>>> I am going to check out the method that you talk about.
>>> For now the fix allow me to boot our board with 8GB it is a good step
>>> for me.
>>>
>>> Thanks
>>> Benoit
>>>
>>> On 07/23/2014 06:32 PM, York Sun wrote:
>>>> Benoit,
>>>>
>>>> If your interest is in initializing DDR for ECC, you don't have use
>>>> dma_meminit(). There is a better and faster way to do so. All Freescale modern
>>>> DDR controllers support this feature. All you have to do is to define these macros
>>>>
>>>> CONFIG_DDR_ECC
>>>> CONFIG_ECC_INIT_VIA_DDRCONTROLLER
>>>> CONFIG_MEM_INIT_VALUE
>>>>
>>>> There are plenty of example for you to follow.
>>>>
>>>> But again, we should fix the DMA function anyway.
>>>>
>> Benoit,
>>
>> Have you tried my suggestion?
>>
>> York
>>
>>
>>
> 
>
diff mbox

Patch

diff -u vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.1.1.1 vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.2
--- vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h:1.1.1.1	Tue Jan  8 10:23:37 2013
+++ vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_ddr_sdram.h	Fri Jul 18 10:31:22 2014
@@ -308,7 +308,7 @@ 
  #endif
  
  #if defined(CONFIG_DDR_ECC)
-extern void ddr_enable_ecc(unsigned int dram_size);
+extern void ddr_enable_ecc(phys_size_t dram_size);
  #endif
  
diff -u vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.1.1.1 vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.2
--- vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h:1.1.1.1	Tue Jan  8 10:23:37 2013
+++ vx3240/u-boot-2012.10/arch/powerpc/include/asm/fsl_dma.h	Fri Jul 18 10:31:22 2014
@@ -134,7 +134,7 @@ 
  void dma_init(void);
  int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
  #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-void dma_meminit(uint val, uint size);
+void dma_meminit(uint val, phys_size_t size);
  #endif
  #endif
  
diff -u vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.1.1.1 vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.2
--- vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c:1.1.1.1	Tue Jan  8 10:23:55 2013
+++ vx3240/u-boot-2012.10/drivers/dma/fsl_dma.c	Fri Jul 18 14:28:31 2014
@@ -113,14 +113,13 @@ 
  
  	while (count) {
  		xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
-
  		out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
  		out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
  #if !defined(CONFIG_MPC83xx)
  		out_dma32(&dma->satr,
-			in_dma32(&dma->satr) | (u32)((u64)src >> 32));
+			in_dma32(&dma->satr) | (u32)(src >> 32));
  		out_dma32(&dma->datr,
-			in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
+			in_dma32(&dma->datr) | (u32)(dest >> 32));
  #endif
  		out_dma32(&dma->bcr, xfer_size);
  		dma_sync();
@@ -152,33 +151,36 @@ 
  #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&	\
  	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) ||		\
  	(defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
-void dma_meminit(uint val, uint size)
+void dma_meminit(uint val, phys_size_t size)
  {
-	uint *p = 0;
-	uint i = 0;
-
-	for (*p = 0; p < (uint *)(8 * 1024); p++) {
-		if (((uint)p & 0x1f) == 0)
-			ppcDcbz((ulong)p);
-
-		*p = (uint)CONFIG_MEM_INIT_VALUE;
-
-		if (((uint)p & 0x1c) == 0x1c)
-			ppcDcbf((ulong)p);
-	}
-
-	dmacpy(0x002000, 0, 0x002000); /* 8K */
-	dmacpy(0x004000, 0, 0x004000); /* 16K */
-	dmacpy(0x008000, 0, 0x008000); /* 32K */
-	dmacpy(0x010000, 0, 0x010000); /* 64K */
-	dmacpy(0x020000, 0, 0x020000); /* 128K */
-	dmacpy(0x040000, 0, 0x040000); /* 256K */
-	dmacpy(0x080000, 0, 0x080000); /* 512K */
-	dmacpy(0x100000, 0, 0x100000); /* 1M */
-	dmacpy(0x200000, 0, 0x200000); /* 2M */
-	dmacpy(0x400000, 0, 0x400000); /* 4M */
-
-	for (i = 1; i < size / 0x800000; i++)
-		dmacpy((0x800000 * i), 0, 0x800000);
+  uint *p = 0;
+  u64 i = 0;
+  phys_addr_t addr;
+
+  for (*p = 0; p < (uint *)(8 * 1024); p++) {
+    if (((uint)p & 0x1f) == 0)
+      ppcDcbz((ulong)p);
+
+    *p = (uint)CONFIG_MEM_INIT_VALUE;
+
+    if (((uint)p & 0x1c) == 0x1c)
+      ppcDcbf((ulong)p);
+  }
+
+  dmacpy(0x002000, 0, 0x002000); /* 8K */
+  dmacpy(0x004000, 0, 0x004000); /* 16K */
+  dmacpy(0x008000, 0, 0x008000); /* 32K */
+  dmacpy(0x010000, 0, 0x010000); /* 64K */
+  dmacpy(0x020000, 0, 0x020000); /* 128K */
+  dmacpy(0x040000, 0, 0x040000); /* 256K */
+  dmacpy(0x080000, 0, 0x080000); /* 512K */
+  dmacpy(0x100000, 0, 0x100000); /* 1M */
+  dmacpy(0x200000, 0, 0x200000); /* 2M */
+  dmacpy(0x400000, 0, 0x400000); /* 4M */
+
+  for (i = 1; i < size / 0x800000; i++) {
+    addr = (phys_addr_t) (i * 0x800000);
+    dmacpy(addr, (phys_addr_t)0, 0x800000);
+  }
  }
  #endif