| Message ID | 1395646841-24416-1-git-send-email-andrew_gabbasov@mentor.com |
|---|---|
| State | Accepted |
| Delegated to: | Pantelis Antoniou |
| Headers | show |
Hi Andrew, On Mar 24, 2014, at 9:40 AM, Andrew Gabbasov wrote: > Calculation of the timeout value should be based on actual clock value, > written to controller registers. Since mmc->tran_speed is either the > maximum allowed speed, or the preliminary value, that is be not yet > set to registers, the actual timeout, taken by the controller, based > on its clock settings, may be much longer than expected, based on > mmc->tran_speed value. In particular it happens at early initialization > stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while > actual clock setting, configured in the controller, is 400kHz. > It's more correct to use mmc->clock value for timeout calculation instead. > > Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> > --- > drivers/mmc/fsl_esdhc.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index 7b146a3..f4d3132 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -221,16 +221,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) > * 2)Timeout period should be minimum 0.250sec as per SD Card spec > * So, Number of SD Clock cycles for 0.25sec should be minimum > * (SD Clock/sec * 0.25 sec) SD Clock cycles > - * = (mmc->tran_speed * 1/4) SD Clock cycles > + * = (mmc->clock * 1/4) SD Clock cycles > * As 1) >= 2) > - * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 > + * => (2^(timeout+13)) >= mmc->clock * 1/4 > * Taking log2 both the sides > - * => timeout + 13 >= log2(mmc->tran_speed/4) > + * => timeout + 13 >= log2(mmc->clock/4) > * Rounding up to next power of 2 > - * => timeout + 13 = log2(mmc->tran_speed/4) + 1 > - * => timeout + 13 = fls(mmc->tran_speed/4) > + * => timeout + 13 = log2(mmc->clock/4) + 1 > + * => timeout + 13 = fls(mmc->clock/4) > */ > - timeout = fls(mmc->tran_speed/4); > + timeout = fls(mmc->clock/4); > timeout -= 13; > > if (timeout > 14) > -- > 1.7.10.4 Thanks Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 7b146a3..f4d3132 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -221,16 +221,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) * 2)Timeout period should be minimum 0.250sec as per SD Card spec * So, Number of SD Clock cycles for 0.25sec should be minimum * (SD Clock/sec * 0.25 sec) SD Clock cycles - * = (mmc->tran_speed * 1/4) SD Clock cycles + * = (mmc->clock * 1/4) SD Clock cycles * As 1) >= 2) - * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * => (2^(timeout+13)) >= mmc->clock * 1/4 * Taking log2 both the sides - * => timeout + 13 >= log2(mmc->tran_speed/4) + * => timeout + 13 >= log2(mmc->clock/4) * Rounding up to next power of 2 - * => timeout + 13 = log2(mmc->tran_speed/4) + 1 - * => timeout + 13 = fls(mmc->tran_speed/4) + * => timeout + 13 = log2(mmc->clock/4) + 1 + * => timeout + 13 = fls(mmc->clock/4) */ - timeout = fls(mmc->tran_speed/4); + timeout = fls(mmc->clock/4); timeout -= 13; if (timeout > 14)
Calculation of the timeout value should be based on actual clock value, written to controller registers. Since mmc->tran_speed is either the maximum allowed speed, or the preliminary value, that is be not yet set to registers, the actual timeout, taken by the controller, based on its clock settings, may be much longer than expected, based on mmc->tran_speed value. In particular it happens at early initialization stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while actual clock setting, configured in the controller, is 400kHz. It's more correct to use mmc->clock value for timeout calculation instead. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> --- drivers/mmc/fsl_esdhc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)