[v4,15/21] target-arm: Add AArch64 ELR_EL1 register.

Add the AArch64 ELR_EL1 register.

Note that this does not live in env->cp15: for KVM migration
compatibility we need to migrate it separately rather than
as part of the system registers, because the KVM-to-userspace
interface puts it in the struct kvm_regs rather than making
them visible via the ONE_REG ioctls.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h     |  2 ++
 target-arm/helper.c  |  4 ++++
 target-arm/kvm64.c   | 15 ++++++++++++++-
 target-arm/machine.c |  7 ++++---
 4 files changed, 24 insertions(+), 4 deletions(-)

On Fri, Mar 7, 2014 at 5:32 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Add the AArch64 ELR_EL1 register.
>
> Note that this does not live in env->cp15: for KVM migration
> compatibility we need to migrate it separately rather than
> as part of the system registers, because the KVM-to-userspace
> interface puts it in the struct kvm_regs rather than making
> them visible via the ONE_REG ioctls.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

(Although my working knowledge of KVM is very limited).

Regards,
Peter

> ---
>  target-arm/cpu.h     |  2 ++
>  target-arm/helper.c  |  4 ++++
>  target-arm/kvm64.c   | 15 ++++++++++++++-
>  target-arm/machine.c |  7 ++++---
>  4 files changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index e51add2..7ef2c71 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -162,6 +162,8 @@ typedef struct CPUARMState {
>      uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
>      uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
>
> +    uint64_t elr_el1; /* AArch64 ELR_EL1 */
> +
>      /* System control coprocessor (cp15) */
>      struct {
>          uint32_t c0_cpuid;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 8d96b5c..812fc73 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1810,6 +1810,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>      { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
>        .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
>        .access = PL1_W, .type = ARM_CP_NOP },
> +    { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_NO_MIGRATE,
> +      .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
> +      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, elr_el1) },
>      REGINFO_SENTINEL
>  };
>
> diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
> index 1b7ca90..ee72748 100644
> --- a/target-arm/kvm64.c
> +++ b/target-arm/kvm64.c
> @@ -144,9 +144,15 @@ int kvm_arch_put_registers(CPUState *cs, int level)
>          return ret;
>      }
>
> +    reg.id = AARCH64_CORE_REG(elr_el1);
> +    reg.addr = (uintptr_t) &env->elr_el1;
> +    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
> +    if (ret) {
> +        return ret;
> +    }
> +
>      /* TODO:
>       * SP_EL1
> -     * ELR_EL1
>       * SPSR[]
>       * FP state
>       * system registers
> @@ -195,6 +201,13 @@ int kvm_arch_get_registers(CPUState *cs)
>          return ret;
>      }
>
> +    reg.id = AARCH64_CORE_REG(elr_el1);
> +    reg.addr = (uintptr_t) &env->elr_el1;
> +    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
> +    if (ret) {
> +        return ret;
> +    }
> +
>      /* TODO: other registers */
>      return ret;
>  }
> diff --git a/target-arm/machine.c b/target-arm/machine.c
> index fc8825e..01d8f83 100644
> --- a/target-arm/machine.c
> +++ b/target-arm/machine.c
> @@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id)
>
>  const VMStateDescription vmstate_arm_cpu = {
>      .name = "cpu",
> -    .version_id = 14,
> -    .minimum_version_id = 14,
> -    .minimum_version_id_old = 14,
> +    .version_id = 15,
> +    .minimum_version_id = 15,
> +    .minimum_version_id_old = 15,
>      .pre_save = cpu_pre_save,
>      .post_load = cpu_post_load,
>      .fields = (VMStateField[]) {
> @@ -243,6 +243,7 @@ const VMStateDescription vmstate_arm_cpu = {
>          VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
>          VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
>          VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
> +        VMSTATE_UINT64(env.elr_el1, ARMCPU),
>          /* The length-check must come before the arrays to avoid
>           * incoming data possibly overflowing the array.
>           */
> --
> 1.9.0
>
>