| Message ID | 1394134385-1727-3-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Fri, Mar 7, 2014 at 5:32 AM, Peter Maydell <peter.maydell@linaro.org> wrote: > Implement the DAIF system register which is a view of the > DAIF bits in PSTATE. To avoid needing a readfn, we widen > the daif field in CPUARMState to uint64_t. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> > --- > target-arm/cpu.h | 2 +- > target-arm/helper.c | 20 ++++++++++++++++++++ > 2 files changed, 21 insertions(+), 1 deletion(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 6252ff3..45eb6a2 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -160,7 +160,7 @@ typedef struct CPUARMState { > uint32_t GE; /* cpsr[19:16] */ > uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ > uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ > - uint32_t daif; /* exception masks, in the bits they are in in PSTATE */ > + uint64_t daif; /* exception masks, in the bits they are in in PSTATE */ > > /* System control coprocessor (cp15) */ > struct { > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 3d65bae..f7168c1 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1593,6 +1593,20 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, > vfp_set_fpsr(env, value); > } > > +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) > +{ > + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { > + return CP_ACCESS_TRAP; > + } > + return CP_ACCESS_OK; > +} > + > +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + env->daif = value & PSTATE_DAIF; > +} > + > static CPAccessResult aa64_cacheop_access(CPUARMState *env, > const ARMCPRegInfo *ri) > { > @@ -1636,6 +1650,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > { .name = "NZCV", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, > .access = PL0_RW, .type = ARM_CP_NZCV }, > + { .name = "DAIF", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, > + .type = ARM_CP_NO_MIGRATE, > + .access = PL0_RW, .accessfn = aa64_daif_access, > + .fieldoffset = offsetof(CPUARMState, daif), > + .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, > { .name = "FPCR", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, > .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, > -- > 1.9.0 > >
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6252ff3..45eb6a2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -160,7 +160,7 @@ typedef struct CPUARMState { uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ - uint32_t daif; /* exception masks, in the bits they are in in PSTATE */ + uint64_t daif; /* exception masks, in the bits they are in in PSTATE */ /* System control coprocessor (cp15) */ struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 3d65bae..f7168c1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1593,6 +1593,20 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, vfp_set_fpsr(env, value); } +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->daif = value & PSTATE_DAIF; +} + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -1636,6 +1650,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "NZCV", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, .access = PL0_RW, .type = ARM_CP_NZCV }, + { .name = "DAIF", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, + .type = ARM_CP_NO_MIGRATE, + .access = PL0_RW, .accessfn = aa64_daif_access, + .fieldoffset = offsetof(CPUARMState, daif), + .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, { .name = "FPCR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
Implement the DAIF system register which is a view of the DAIF bits in PSTATE. To avoid needing a readfn, we widen the daif field in CPUARMState to uint64_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/cpu.h | 2 +- target-arm/helper.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-)