| Message ID | 1391577495-22170-1-git-send-email-rajeshwari.s@samsung.com |
|---|---|
| State | Accepted |
| Delegated to: | Pantelis Antoniou |
| Headers | show |
Hi All, CCing Jaehoon Chung. Regards, Rajeshwari On Wed, Feb 5, 2014 at 10:48 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote: > From: Rajeshwari S Shinde <rajeshwari.s@samsung.com> > > This patch corrects the divider value written to CLKDIV register. > Since SDCLKIN is divided inside controller by the DIVRATIO value set > in the CLKSEL register, we need to use the same output clock value to > calculate the CLKDIV value. > as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) > > Input parameter to mmc_clk is changed to dwmci_host, since > we need the same to read DWMCI_CLKSEL register. > > This improves the read timing values for channel 0 on SMDK5250 > from 0.288sec to 0.144sec > > Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> > --- > arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ > drivers/mmc/dw_mmc.c | 2 +- > drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- > include/dwmmc.h | 2 +- > 4 files changed, 21 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h > index 09d739d..a7ca12c 100644 > --- a/arch/arm/include/asm/arch-exynos/dwmmc.h > +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h > @@ -23,6 +23,10 @@ > #define MPSCTRL_ENCRYPTION (0x1<<1) > #define MPSCTRL_VALID (0x1<<0) > > +/* CLKSEL Register */ > +#define DWMCI_DIVRATIO_BIT 24 > +#define DWMCI_DIVRATIO_MASK 0x7 > + > #ifdef CONFIG_OF_CONTROL > int exynos_dwmmc_init(const void *blob); > #endif > diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c > index 4cec5aa..d45c15c 100644 > --- a/drivers/mmc/dw_mmc.c > +++ b/drivers/mmc/dw_mmc.c > @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) > * host->bus_hz should be set from user. > */ > if (host->get_mmc_clk) > - sclk = host->get_mmc_clk(host->dev_index); > + sclk = host->get_mmc_clk(host); > else if (host->bus_hz) > sclk = host->bus_hz; > else { > diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c > index b3e5c5e..de8cdcc 100644 > --- a/drivers/mmc/exynos_dw_mmc.c > +++ b/drivers/mmc/exynos_dw_mmc.c > @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) > dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); > } > > -unsigned int exynos_dwmci_get_clk(int dev_index) > +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) > { > - return get_mmc_clk(dev_index); > + unsigned long sclk; > + int8_t clk_div; > + > + /* > + * Since SDCLKIN is divided inside controller by the DIVRATIO > + * value set in the CLKSEL register, we need to use the same output > + * clock value to calculate the CLKDIV value. > + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) > + */ > + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) > + & DWMCI_DIVRATIO_MASK) + 1; > + sclk = get_mmc_clk(host->dev_index); > + > + return sclk / clk_div; > } > > static void exynos_dwmci_board_init(struct dwmci_host *host) > diff --git a/include/dwmmc.h b/include/dwmmc.h > index a02dd67..b641558 100644 > --- a/include/dwmmc.h > +++ b/include/dwmmc.h > @@ -142,7 +142,7 @@ struct dwmci_host { > > void (*clksel)(struct dwmci_host *host); > void (*board_init)(struct dwmci_host *host); > - unsigned int (*get_mmc_clk)(int dev_index); > + unsigned int (*get_mmc_clk)(struct dwmci_host *host); > }; > > struct dwmci_idmac { > -- > 1.7.12.4 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
Hi. Right, It's reasonable. Looks good to me. Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung On 02/05/2014 02:58 PM, Rajeshwari Birje wrote: > Hi All, > > CCing Jaehoon Chung. > > Regards, > Rajeshwari > > On Wed, Feb 5, 2014 at 10:48 AM, Rajeshwari Shinde > <rajeshwari.s@samsung.com> wrote: >> From: Rajeshwari S Shinde <rajeshwari.s@samsung.com> >> >> This patch corrects the divider value written to CLKDIV register. >> Since SDCLKIN is divided inside controller by the DIVRATIO value set >> in the CLKSEL register, we need to use the same output clock value to >> calculate the CLKDIV value. >> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) >> >> Input parameter to mmc_clk is changed to dwmci_host, since >> we need the same to read DWMCI_CLKSEL register. >> >> This improves the read timing values for channel 0 on SMDK5250 >> from 0.288sec to 0.144sec >> >> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> >> --- >> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ >> drivers/mmc/dw_mmc.c | 2 +- >> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- >> include/dwmmc.h | 2 +- >> 4 files changed, 21 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h >> index 09d739d..a7ca12c 100644 >> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h >> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h >> @@ -23,6 +23,10 @@ >> #define MPSCTRL_ENCRYPTION (0x1<<1) >> #define MPSCTRL_VALID (0x1<<0) >> >> +/* CLKSEL Register */ >> +#define DWMCI_DIVRATIO_BIT 24 >> +#define DWMCI_DIVRATIO_MASK 0x7 >> + >> #ifdef CONFIG_OF_CONTROL >> int exynos_dwmmc_init(const void *blob); >> #endif >> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c >> index 4cec5aa..d45c15c 100644 >> --- a/drivers/mmc/dw_mmc.c >> +++ b/drivers/mmc/dw_mmc.c >> @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) >> * host->bus_hz should be set from user. >> */ >> if (host->get_mmc_clk) >> - sclk = host->get_mmc_clk(host->dev_index); >> + sclk = host->get_mmc_clk(host); >> else if (host->bus_hz) >> sclk = host->bus_hz; >> else { >> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c >> index b3e5c5e..de8cdcc 100644 >> --- a/drivers/mmc/exynos_dw_mmc.c >> +++ b/drivers/mmc/exynos_dw_mmc.c >> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) >> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); >> } >> >> -unsigned int exynos_dwmci_get_clk(int dev_index) >> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) >> { >> - return get_mmc_clk(dev_index); >> + unsigned long sclk; >> + int8_t clk_div; >> + >> + /* >> + * Since SDCLKIN is divided inside controller by the DIVRATIO >> + * value set in the CLKSEL register, we need to use the same output >> + * clock value to calculate the CLKDIV value. >> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) >> + */ >> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) >> + & DWMCI_DIVRATIO_MASK) + 1; >> + sclk = get_mmc_clk(host->dev_index); >> + >> + return sclk / clk_div; >> } >> >> static void exynos_dwmci_board_init(struct dwmci_host *host) >> diff --git a/include/dwmmc.h b/include/dwmmc.h >> index a02dd67..b641558 100644 >> --- a/include/dwmmc.h >> +++ b/include/dwmmc.h >> @@ -142,7 +142,7 @@ struct dwmci_host { >> >> void (*clksel)(struct dwmci_host *host); >> void (*board_init)(struct dwmci_host *host); >> - unsigned int (*get_mmc_clk)(int dev_index); >> + unsigned int (*get_mmc_clk)(struct dwmci_host *host); >> }; >> >> struct dwmci_idmac { >> -- >> 1.7.12.4 >> >> _______________________________________________ >> U-Boot mailing list >> U-Boot@lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot > > >
Hi Pantelis Antoniou, Please do let me know if any coments on the same. Regards, Rajeshwari On Thu, Feb 6, 2014 at 7:24 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote: > Hi. > > Right, It's reasonable. Looks good to me. > > Acked-by: Jaehoon Chung <jh80.chung@samsung.com> > > Best Regards, > Jaehoon Chung > > On 02/05/2014 02:58 PM, Rajeshwari Birje wrote: >> Hi All, >> >> CCing Jaehoon Chung. >> >> Regards, >> Rajeshwari >> >> On Wed, Feb 5, 2014 at 10:48 AM, Rajeshwari Shinde >> <rajeshwari.s@samsung.com> wrote: >>> From: Rajeshwari S Shinde <rajeshwari.s@samsung.com> >>> >>> This patch corrects the divider value written to CLKDIV register. >>> Since SDCLKIN is divided inside controller by the DIVRATIO value set >>> in the CLKSEL register, we need to use the same output clock value to >>> calculate the CLKDIV value. >>> as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) >>> >>> Input parameter to mmc_clk is changed to dwmci_host, since >>> we need the same to read DWMCI_CLKSEL register. >>> >>> This improves the read timing values for channel 0 on SMDK5250 >>> from 0.288sec to 0.144sec >>> >>> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> >>> --- >>> arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ >>> drivers/mmc/dw_mmc.c | 2 +- >>> drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- >>> include/dwmmc.h | 2 +- >>> 4 files changed, 21 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h >>> index 09d739d..a7ca12c 100644 >>> --- a/arch/arm/include/asm/arch-exynos/dwmmc.h >>> +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h >>> @@ -23,6 +23,10 @@ >>> #define MPSCTRL_ENCRYPTION (0x1<<1) >>> #define MPSCTRL_VALID (0x1<<0) >>> >>> +/* CLKSEL Register */ >>> +#define DWMCI_DIVRATIO_BIT 24 >>> +#define DWMCI_DIVRATIO_MASK 0x7 >>> + >>> #ifdef CONFIG_OF_CONTROL >>> int exynos_dwmmc_init(const void *blob); >>> #endif >>> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c >>> index 4cec5aa..d45c15c 100644 >>> --- a/drivers/mmc/dw_mmc.c >>> +++ b/drivers/mmc/dw_mmc.c >>> @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) >>> * host->bus_hz should be set from user. >>> */ >>> if (host->get_mmc_clk) >>> - sclk = host->get_mmc_clk(host->dev_index); >>> + sclk = host->get_mmc_clk(host); >>> else if (host->bus_hz) >>> sclk = host->bus_hz; >>> else { >>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c >>> index b3e5c5e..de8cdcc 100644 >>> --- a/drivers/mmc/exynos_dw_mmc.c >>> +++ b/drivers/mmc/exynos_dw_mmc.c >>> @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) >>> dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); >>> } >>> >>> -unsigned int exynos_dwmci_get_clk(int dev_index) >>> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) >>> { >>> - return get_mmc_clk(dev_index); >>> + unsigned long sclk; >>> + int8_t clk_div; >>> + >>> + /* >>> + * Since SDCLKIN is divided inside controller by the DIVRATIO >>> + * value set in the CLKSEL register, we need to use the same output >>> + * clock value to calculate the CLKDIV value. >>> + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) >>> + */ >>> + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) >>> + & DWMCI_DIVRATIO_MASK) + 1; >>> + sclk = get_mmc_clk(host->dev_index); >>> + >>> + return sclk / clk_div; >>> } >>> >>> static void exynos_dwmci_board_init(struct dwmci_host *host) >>> diff --git a/include/dwmmc.h b/include/dwmmc.h >>> index a02dd67..b641558 100644 >>> --- a/include/dwmmc.h >>> +++ b/include/dwmmc.h >>> @@ -142,7 +142,7 @@ struct dwmci_host { >>> >>> void (*clksel)(struct dwmci_host *host); >>> void (*board_init)(struct dwmci_host *host); >>> - unsigned int (*get_mmc_clk)(int dev_index); >>> + unsigned int (*get_mmc_clk)(struct dwmci_host *host); >>> }; >>> >>> struct dwmci_idmac { >>> -- >>> 1.7.12.4 >>> >>> _______________________________________________ >>> U-Boot mailing list >>> U-Boot@lists.denx.de >>> http://lists.denx.de/mailman/listinfo/u-boot >> >> >> >
Hi Rajesh, Sorry for the delay, patch looks good. On Feb 5, 2014, at 7:18 AM, Rajeshwari Shinde wrote: > From: Rajeshwari S Shinde <rajeshwari.s@samsung.com> > > This patch corrects the divider value written to CLKDIV register. > Since SDCLKIN is divided inside controller by the DIVRATIO value set > in the CLKSEL register, we need to use the same output clock value to > calculate the CLKDIV value. > as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) > > Input parameter to mmc_clk is changed to dwmci_host, since > we need the same to read DWMCI_CLKSEL register. > > This improves the read timing values for channel 0 on SMDK5250 > from 0.288sec to 0.144sec > > Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> > --- > arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ > drivers/mmc/dw_mmc.c | 2 +- > drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- > include/dwmmc.h | 2 +- > 4 files changed, 21 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h > index 09d739d..a7ca12c 100644 > --- a/arch/arm/include/asm/arch-exynos/dwmmc.h > +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h > @@ -23,6 +23,10 @@ > #define MPSCTRL_ENCRYPTION (0x1<<1) > #define MPSCTRL_VALID (0x1<<0) > > +/* CLKSEL Register */ > +#define DWMCI_DIVRATIO_BIT 24 > +#define DWMCI_DIVRATIO_MASK 0x7 > + > #ifdef CONFIG_OF_CONTROL > int exynos_dwmmc_init(const void *blob); > #endif > diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c > index 4cec5aa..d45c15c 100644 > --- a/drivers/mmc/dw_mmc.c > +++ b/drivers/mmc/dw_mmc.c > @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) > * host->bus_hz should be set from user. > */ > if (host->get_mmc_clk) > - sclk = host->get_mmc_clk(host->dev_index); > + sclk = host->get_mmc_clk(host); > else if (host->bus_hz) > sclk = host->bus_hz; > else { > diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c > index b3e5c5e..de8cdcc 100644 > --- a/drivers/mmc/exynos_dw_mmc.c > +++ b/drivers/mmc/exynos_dw_mmc.c > @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) > dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); > } > > -unsigned int exynos_dwmci_get_clk(int dev_index) > +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) > { > - return get_mmc_clk(dev_index); > + unsigned long sclk; > + int8_t clk_div; > + > + /* > + * Since SDCLKIN is divided inside controller by the DIVRATIO > + * value set in the CLKSEL register, we need to use the same output > + * clock value to calculate the CLKDIV value. > + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) > + */ > + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) > + & DWMCI_DIVRATIO_MASK) + 1; > + sclk = get_mmc_clk(host->dev_index); > + > + return sclk / clk_div; > } > > static void exynos_dwmci_board_init(struct dwmci_host *host) > diff --git a/include/dwmmc.h b/include/dwmmc.h > index a02dd67..b641558 100644 > --- a/include/dwmmc.h > +++ b/include/dwmmc.h > @@ -142,7 +142,7 @@ struct dwmci_host { > > void (*clksel)(struct dwmci_host *host); > void (*board_init)(struct dwmci_host *host); > - unsigned int (*get_mmc_clk)(int dev_index); > + unsigned int (*get_mmc_clk)(struct dwmci_host *host); > }; > > struct dwmci_idmac { > -- > 1.7.12.4 > Applied, Thanks Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 09d739d..a7ca12c 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -23,6 +23,10 @@ #define MPSCTRL_ENCRYPTION (0x1<<1) #define MPSCTRL_VALID (0x1<<0) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aa..d45c15c 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host->dev_index); + sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b3e5c5e..de8cdcc 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) diff --git a/include/dwmmc.h b/include/dwmmc.h index a02dd67..b641558 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -142,7 +142,7 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - unsigned int (*get_mmc_clk)(int dev_index); + unsigned int (*get_mmc_clk)(struct dwmci_host *host); }; struct dwmci_idmac {