| Message ID | 1391183143-30724-28-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell <peter.maydell@linaro.org> wrote: > Implement the AArch64 view of the system control register SCTLR_EL1. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> > --- > target-arm/cpu.h | 2 +- > target-arm/helper.c | 3 ++- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index a08c02b..1fb9675 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -169,7 +169,7 @@ typedef struct CPUARMState { > struct { > uint32_t c0_cpuid; > uint64_t c0_cssel; /* Cache size selection. */ > - uint32_t c1_sys; /* System control register. */ > + uint64_t c1_sys; /* System control register. */ > uint32_t c1_coproc; /* Coprocessor access register. */ > uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ > uint32_t c1_scr; /* secure config register. */ > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 32bface..7f466d6 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1973,7 +1973,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) > /* Generic registers whose values depend on the implementation */ > { > ARMCPRegInfo sctlr = { > - .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, > + .name = "SCTLR", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, > .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), > .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, > .raw_writefn = raw_write, > -- > 1.8.5 > >
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a08c02b..1fb9675 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -169,7 +169,7 @@ typedef struct CPUARMState { struct { uint32_t c0_cpuid; uint64_t c0_cssel; /* Cache size selection. */ - uint32_t c1_sys; /* System control register. */ + uint64_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 32bface..7f466d6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1973,7 +1973,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr = { - .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, + .name = "SCTLR", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys), .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, .raw_writefn = raw_write,
Implement the AArch64 view of the system control register SCTLR_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/cpu.h | 2 +- target-arm/helper.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)