[1/5] powerpc/85xx/dts: add third elo3 dma component

Add elo3-dma-2.dtsi to support the third DMA controller.
This is used on T2080, T4240, etc.

MPIC registers for internal interrupts is non-continous in address, any
internal interrupt number greater than 159 should be added (16+208) to work,
adding 16 is due to external interrupts as usual, adding 208 is due to
non-continous MPIC register space.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
---
 arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi | 82 +++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi

Shengzhou,
I canceled my patch http://patchwork.ozlabs.org/patch/295157/ because 
the original wrong elo3-dma-2.dtsi hadn't been merged.
But please pay attention to comments from Scott about my changes of 
adding 208 for some interrupts, and take some actions if needed, or 
further discussions.

Below comments form Scott:
"The FSL MPIC binding should be updated to point out how this works.
Technically it's not a change to the binding itself, since it's defined
in terms of register offset, but the explanatory text says "So interrupt
0 is at offset 0x0, interrupt 1 is at offset 0x20, and so on." which is
not accurate for these new high interrupt numbers."


On 12/11/2013 07:19 PM, Shengzhou Liu wrote:
> Add elo3-dma-2.dtsi to support the third DMA controller.
> This is used on T2080, T4240, etc.
>
> MPIC registers for internal interrupts is non-continous in address, any
> internal interrupt number greater than 159 should be added (16+208) to work,
> adding 16 is due to external interrupts as usual, adding 208 is due to
> non-continous MPIC register space.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
> ---
>   arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi | 82 +++++++++++++++++++++++++++++++
>   1 file changed, 82 insertions(+)
>   create mode 100644 arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
>
> diff --git a/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
> new file mode 100644
> index 0000000..d3cc8d0
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
> @@ -0,0 +1,82 @@
> +/*
> + * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
> + *
> + * Copyright 2013 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyright
> + *       notice, this list of conditions and the following disclaimer in the
> + *       documentation and/or other materials provided with the distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote products
> + *       derived from this software without specific prior written permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of the
> + * GNU General Public License ("GPL") as published by the Free Software
> + * Foundation, either version 2 of that License or (at your option) any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +dma2: dma@102300 {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "fsl,elo3-dma";
> +	reg = <0x102300 0x4>,
> +	      <0x102600 0x4>;
> +	ranges = <0x0 0x102100 0x500>;
> +	dma-channel@0 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x0 0x80>;
> +		interrupts = <464 2 0 0>;
> +	};
> +	dma-channel@80 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x80 0x80>;
> +		interrupts = <465 2 0 0>;
> +	};
> +	dma-channel@100 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x100 0x80>;
> +		interrupts = <466 2 0 0>;
> +	};
> +	dma-channel@180 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x180 0x80>;
> +		interrupts = <467 2 0 0>;
> +	};
> +	dma-channel@300 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x300 0x80>;
> +		interrupts = <468 2 0 0>;
> +	};
> +	dma-channel@380 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x380 0x80>;
> +		interrupts = <469 2 0 0>;
> +	};
> +	dma-channel@400 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x400 0x80>;
> +		interrupts = <470 2 0 0>;
> +	};
> +	dma-channel@480 {
> +		compatible = "fsl,eloplus-dma-channel";
> +		reg = <0x480 0x80>;
> +		interrupts = <471 2 0 0>;
> +	};
> +};

> -----Original Message-----
> From: Hongbo Zhang [mailto:hongbo.zhang@freescale.com]
> Sent: Thursday, December 12, 2013 5:57 PM
> To: Liu Shengzhou-B36685; linuxppc-dev@lists.ozlabs.org; Wood Scott-
> B07421
> Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
> 
> Shengzhou,
> I canceled my patch http://patchwork.ozlabs.org/patch/295157/ because the
> original wrong elo3-dma-2.dtsi hadn't been merged.
> But please pay attention to comments from Scott about my changes of
> adding 208 for some interrupts, and take some actions if needed, or
> further discussions.
> 
> Below comments form Scott:
> "The FSL MPIC binding should be updated to point out how this works.
> Technically it's not a change to the binding itself, since it's defined
> in terms of register offset, but the explanatory text says "So interrupt
> 0 is at offset 0x0, interrupt 1 is at offset 0x20, and so on." which is
> not accurate for these new high interrupt numbers."
> 
Hongbo,
Could you update FSL MPIC binding as Scott pointed out?

thanks,
Shengzhou

On 12/13/2013 01:43 PM, Liu Shengzhou-B36685 wrote:
>
>> -----Original Message-----
>> From: Hongbo Zhang [mailto:hongbo.zhang@freescale.com]
>> Sent: Thursday, December 12, 2013 5:57 PM
>> To: Liu Shengzhou-B36685; linuxppc-dev@lists.ozlabs.org; Wood Scott-
>> B07421
>> Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
>>
>> Shengzhou,
>> I canceled my patch http://patchwork.ozlabs.org/patch/295157/ because the
>> original wrong elo3-dma-2.dtsi hadn't been merged.
>> But please pay attention to comments from Scott about my changes of
>> adding 208 for some interrupts, and take some actions if needed, or
>> further discussions.
>>
>> Below comments form Scott:
>> "The FSL MPIC binding should be updated to point out how this works.
>> Technically it's not a change to the binding itself, since it's defined
>> in terms of register offset, but the explanatory text says "So interrupt
>> 0 is at offset 0x0, interrupt 1 is at offset 0x20, and so on." which is
>> not accurate for these new high interrupt numbers."
>>
> Hongbo,
> Could you update FSL MPIC binding as Scott pointed out?

We only need to add more explanatory text after the sentence Scott 
pointed out, like:
"But for some hardwares, the MPIC registers for interrupts are not 
continuous in address,  in such cases, an offset can be added to the 
interrupt number to skip the registers which is not for interrupts."

Scott, is that OK?

Thanks.

> thanks,
> Shengzhou

On Mon, 2013-12-16 at 17:12 +0800, Hongbo Zhang wrote:
> On 12/13/2013 01:43 PM, Liu Shengzhou-B36685 wrote:
> >
> >> -----Original Message-----
> >> From: Hongbo Zhang [mailto:hongbo.zhang@freescale.com]
> >> Sent: Thursday, December 12, 2013 5:57 PM
> >> To: Liu Shengzhou-B36685; linuxppc-dev@lists.ozlabs.org; Wood Scott-
> >> B07421
> >> Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
> >>
> >> Shengzhou,
> >> I canceled my patch http://patchwork.ozlabs.org/patch/295157/ because the
> >> original wrong elo3-dma-2.dtsi hadn't been merged.
> >> But please pay attention to comments from Scott about my changes of
> >> adding 208 for some interrupts, and take some actions if needed, or
> >> further discussions.
> >>
> >> Below comments form Scott:
> >> "The FSL MPIC binding should be updated to point out how this works.
> >> Technically it's not a change to the binding itself, since it's defined
> >> in terms of register offset, but the explanatory text says "So interrupt
> >> 0 is at offset 0x0, interrupt 1 is at offset 0x20, and so on." which is
> >> not accurate for these new high interrupt numbers."
> >>
> > Hongbo,
> > Could you update FSL MPIC binding as Scott pointed out?
> 
> We only need to add more explanatory text after the sentence Scott 
> pointed out, like:
> "But for some hardwares, the MPIC registers for interrupts are not 
> continuous in address,  in such cases, an offset can be added to the 
> interrupt number to skip the registers which is not for interrupts."
> 
> Scott, is that OK?

Actually, I misread what that sentence actually says, and it's correct
as is -- but not as helpful as it could be.

I'd add this new paragraph instead:

For example, internal interrupt 0 is at offset 0x200 and thus is
interrupt 16 in the device tree.  MSI bank A interrupt 0 is at offset
0x1c00, and thus is interrupt 224.  MPIC v4.3 adds a new discontiguous
address range for internal interrupts, so internal interrupt 160 is at
offset 0x3000, and thus is interrupt 384.

-Scott