| Message ID | 20131127110406.6DC8E1A504F@localhost.localdomain (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Wed, 2013-11-27 at 12:04 +0100, Christophe Leroy wrote: > Today, the only way to load kernels whose size is greater than 8Mbytes is to > activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is > limited to 8Mbytes. This patch sets up 24 Mbytes of initial memory regardless > of whether CONFIG_PIN_TLB is active or not. It allows to load "big" kernels > (for instance when activating CONFIG_LOCKDEP_SUPPORT) without having > to activate CONFIG_PIN_TLB. So, what happens on boards with less than 24M memory present? Even if you avoid explicitly referencing those addresses, what if there is a speculative access -- or does 8xx not do that? -Scott
Le 06/12/2013 20:09, Scott Wood a écrit : > On Wed, 2013-11-27 at 12:04 +0100, Christophe Leroy wrote: >> Today, the only way to load kernels whose size is greater than 8Mbytes is to >> activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is >> limited to 8Mbytes. This patch sets up 24 Mbytes of initial memory regardless >> of whether CONFIG_PIN_TLB is active or not. It allows to load "big" kernels >> (for instance when activating CONFIG_LOCKDEP_SUPPORT) without having >> to activate CONFIG_PIN_TLB. > So, what happens on boards with less than 24M memory present? Even if > you avoid explicitly referencing those addresses, what if there is a > speculative access -- or does 8xx not do that? > > -Scott > Function setup_initial_memory_limit() in mm/init_32.c defines the limits based on the parameters given by the bootloader. As far as I know, the 8xx doesn't do speculative access just because an area is loaded in a TLB Entry. Christophe --- Ce courrier électronique ne contient aucun virus ou logiciel malveillant parce que la protection avast! Antivirus est active. http://www.avast.com
On Sat, 2013-12-07 at 10:39 +0100, christophe leroy wrote: > Function setup_initial_memory_limit() in mm/init_32.c defines the > limits > based on the parameters given by the bootloader. > As far as I know, the 8xx doesn't do speculative access just because > an area is loaded in a TLB Entry. Speculative accesses are ... speculative :-) The address used for such an access can be anything really. So yes, architecturally, powerpc processors can access *anything* speculatively just because there's a valid non-garded translation. Whether the 8xx does it at all, I don't know. 44x originally did but that was so buggy that we had to force G on all mappings (until later versions of the core just burned the feature out). Pretty much all other powerpc's do it. Cheers, Ben.
diff -ur a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -841,11 +841,12 @@ ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ mtspr SPRN_MD_RPN, r8 -#ifdef CONFIG_PIN_TLB /* Map two more 8M kernel data pages. */ +#ifdef CONFIG_PIN_TLB addi r10, r10, 0x0100 mtspr SPRN_MD_CTR, r10 +#endif lis r8, KERNELBASE@h /* Create vaddr for TLB */ addis r8, r8, 0x0080 /* Add 8M */ @@ -858,15 +859,16 @@ addis r11, r11, 0x0080 /* Add 8M */ mtspr SPRN_MD_RPN, r11 +#ifdef CONFIG_PIN_TLB addi r10, r10, 0x0100 mtspr SPRN_MD_CTR, r10 +#endif addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 addis r11, r11, 0x0080 /* Add 8M */ mtspr SPRN_MD_RPN, r11 -#endif /* Since the cache is enabled according to the information we * just loaded into the TLB, invalidate and enable the caches here. diff -ur a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c --- a/arch/powerpc/mm/init_32.c +++ b/arch/powerpc/mm/init_32.c @@ -213,12 +213,7 @@ */ BUG_ON(first_memblock_base != 0); -#ifdef CONFIG_PIN_TLB /* 8xx can only access 24MB at the moment */ memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000)); -#else - /* 8xx can only access 8MB at the moment */ - memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000)); -#endif } #endif /* CONFIG_8xx */
Today, the only way to load kernels whose size is greater than 8Mbytes is to activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is limited to 8Mbytes. This patch sets up 24 Mbytes of initial memory regardless of whether CONFIG_PIN_TLB is active or not. It allows to load "big" kernels (for instance when activating CONFIG_LOCKDEP_SUPPORT) without having to activate CONFIG_PIN_TLB. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>