Patchwork powerpc/85xx: Fix ethernet link detection on MPC8569E-MDS boards

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Submitter Anton Vorontsov
Date June 24, 2009, 4:30 p.m.
Message ID <20090624163028.GA18825@oksana.dev.rtsoft.ru>
Download mbox | patch
Permalink /patch/29134/
State Accepted
Delegated to: Kumar Gala
Headers show

Comments

Anton Vorontsov - June 24, 2009, 4:30 p.m.
Linux isn't able to detect link changes on ethernet ports that were
used by U-Boot. This is because U-Boot wrongly clears interrupt
polarity bit (INTPOL, 0x400) in the extended status register (EXT_SR,
0x1b) of Marvell PHYs.

There is no easy way for PHY drivers to know IRQ line polarity (we
could extract it from the device tree and pass it to phydevs, but
that'll be quite a lot of work), so for now just reset the PHYs to
their default states.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
Anton Vorontsov - July 14, 2009, 1:35 p.m.
On Wed, Jun 24, 2009 at 08:30:28PM +0400, Anton Vorontsov wrote:
> Linux isn't able to detect link changes on ethernet ports that were
> used by U-Boot. This is because U-Boot wrongly clears interrupt
> polarity bit (INTPOL, 0x400) in the extended status register (EXT_SR,
> 0x1b) of Marvell PHYs.
> 
> There is no easy way for PHY drivers to know IRQ line polarity (we
> could extract it from the device tree and pass it to phydevs, but
> that'll be quite a lot of work), so for now just reset the PHYs to
> their default states.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---

I think this should be safe for 2.6.31...

Thanks,

>  arch/powerpc/platforms/85xx/mpc85xx_mds.c |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> index 3268c95..34664c0 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> @@ -223,6 +223,19 @@ static void __init mpc85xx_mds_setup_arch(void)
>  			/* Turn UCC1 & UCC2 on */
>  			setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
>  			setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
> +		} else if (machine_is(mpc8569_mds)) {
> +#define BCSR7_UCC12_GETHnRST	(0x1 << 2)
> +#define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
> +			/*
> +			 * U-Boot mangles interrupt polarity for Marvell PHYs,
> +			 * so reset built-in and UEM Marvell PHYs, this puts
> +			 * the PHYs into their normal state.
> +			 */
> +			clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
> +			setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
> +
> +			setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
> +			clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
>  		}
>  		iounmap(bcsr_regs);
>  	}
> -- 
> 1.6.3.1
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
Kumar Gala - July 30, 2009, 4:14 a.m.
On Jun 24, 2009, at 11:30 AM, Anton Vorontsov wrote:

> Linux isn't able to detect link changes on ethernet ports that were
> used by U-Boot. This is because U-Boot wrongly clears interrupt
> polarity bit (INTPOL, 0x400) in the extended status register (EXT_SR,
> 0x1b) of Marvell PHYs.
>
> There is no easy way for PHY drivers to know IRQ line polarity (we
> could extract it from the device tree and pass it to phydevs, but
> that'll be quite a lot of work), so for now just reset the PHYs to
> their default states.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> arch/powerpc/platforms/85xx/mpc85xx_mds.c |   13 +++++++++++++
> 1 files changed, 13 insertions(+), 0 deletions(-)

applied to merge

- k

Patch

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 3268c95..34664c0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -223,6 +223,19 @@  static void __init mpc85xx_mds_setup_arch(void)
 			/* Turn UCC1 & UCC2 on */
 			setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 			setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+		} else if (machine_is(mpc8569_mds)) {
+#define BCSR7_UCC12_GETHnRST	(0x1 << 2)
+#define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
+			/*
+			 * U-Boot mangles interrupt polarity for Marvell PHYs,
+			 * so reset built-in and UEM Marvell PHYs, this puts
+			 * the PHYs into their normal state.
+			 */
+			clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+			setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+			setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+			clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 		}
 		iounmap(bcsr_regs);
 	}