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[2/2] target-arm: Avoid "1 << 31" undefined behaviour

Message ID 1377274359-8707-3-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell Aug. 23, 2013, 4:12 p.m. UTC 
Avoid the undefined behaviour of "1 << 31" by using 1U to make
the shift be of an unsigned value rather than shifting into the
sign bit of a signed integer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h    |    2 +-
 target-arm/helper.c |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

Richard Henderson Aug. 23, 2013, 6:11 p.m. UTC | #1 
On 08/23/2013 09:12 AM, Peter Maydell wrote:
>  #define CPSR_V (1 << 28)
>  #define CPSR_C (1 << 29)
>  #define CPSR_Z (1 << 30)
> -#define CPSR_N (1 << 31)
> +#define CPSR_N (1U << 31)
>  #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)

You'd be better off making all of the CPSR bits unsigned, I think.



r~
Peter Maydell Aug. 24, 2013, 10:38 a.m. UTC | #2 
On 23 August 2013 19:11, Richard Henderson <rth@twiddle.net> wrote:
> On 08/23/2013 09:12 AM, Peter Maydell wrote:
>>  #define CPSR_V (1 << 28)
>>  #define CPSR_C (1 << 29)
>>  #define CPSR_Z (1 << 30)
>> -#define CPSR_N (1 << 31)
>> +#define CPSR_N (1U << 31)
>>  #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
>
> You'd be better off making all of the CPSR bits unsigned, I think.

Agreed; let's be consistent.

-- PMM
diff mbox

Patch

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f2abdf3..f3bd501 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -285,7 +285,7 @@  int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 #define CPSR_V (1 << 28)
 #define CPSR_C (1 << 29)
 #define CPSR_Z (1 << 30)
-#define CPSR_N (1 << 31)
+#define CPSR_N (1U << 31)
 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 
 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f4e1b06..b13edf1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -972,7 +972,7 @@  static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 static inline bool extended_addresses_enabled(CPUARMState *env)
 {
     return arm_feature(env, ARM_FEATURE_LPAE)
-        && (env->cp15.c2_control & (1 << 31));
+        && (env->cp15.c2_control & (1U << 31));
 }
 
 static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@@ -1385,7 +1385,7 @@  static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
      * so these bits always RAZ.
      */
     if (arm_feature(env, ARM_FEATURE_V7MP)) {
-        mpidr |= (1 << 31);
+        mpidr |= (1U << 31);
         /* Cores which are uniprocessor (non-coherent)
          * but still implement the MP extensions set
          * bit 30. (For instance, A9UP.) However we do