[2/6] xics: add pre_save/post_load/cpu_setup dispatchers

The upcoming support of in-kernel XICS will redefine migration callbacks
for both ICS and ICP so classes and callback pointers are added.

This adds a cpu_setup callback to the XICS device class (as XICS-KVM
will do it different) and xics_dispatch_cpu_setup(). This also moves
the place where xics_dispatch_cpu_setup() is called a bit further to
have VCPU initialized (required for XICS-KVM).

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
 hw/intc/xics.c        | 61 +++++++++++++++++++++++++++++++++++++++++++++++----
 hw/ppc/spapr.c        |  4 ++--
 include/hw/ppc/xics.h | 46 +++++++++++++++++++++++++++++++++++++-
 3 files changed, 104 insertions(+), 7 deletions(-)

Am 06.08.2013 10:27, schrieb Alexey Kardashevskiy:
> The upcoming support of in-kernel XICS will redefine migration callbacks
> for both ICS and ICP so classes and callback pointers are added.
> 
> This adds a cpu_setup callback to the XICS device class (as XICS-KVM
> will do it different) and xics_dispatch_cpu_setup(). This also moves
> the place where xics_dispatch_cpu_setup() is called a bit further to
> have VCPU initialized (required for XICS-KVM).
> 
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
>  hw/intc/xics.c        | 61 +++++++++++++++++++++++++++++++++++++++++++++++----
>  hw/ppc/spapr.c        |  4 ++--
>  include/hw/ppc/xics.h | 46 +++++++++++++++++++++++++++++++++++++-
>  3 files changed, 104 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index 6b3c071..c5dad2f 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -153,11 +153,35 @@ static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)
>      }
>  }
>  
> +static void icp_dispatch_pre_save(void *opaque)
> +{
> +    ICPState *ss = opaque;
> +    ICPStateClass *info = ICP_GET_CLASS(ss);
> +
> +    if (info->pre_save) {
> +        info->pre_save(ss);
> +    }
> +}
> +
> +static int icp_dispatch_post_load(void *opaque, int version_id)
> +{
> +    ICPState *ss = opaque;
> +    ICPStateClass *info = ICP_GET_CLASS(ss);
> +
> +    if (info->post_load) {
> +        return info->post_load(ss);
> +    }
> +
> +    return 0;
> +}
> +
>  static const VMStateDescription vmstate_icp_server = {
>      .name = "icp/server",
>      .version_id = 1,
>      .minimum_version_id = 1,
>      .minimum_version_id_old = 1,
> +    .pre_save = icp_dispatch_pre_save,
> +    .post_load = icp_dispatch_post_load,
>      .fields      = (VMStateField []) {
>          /* Sanity check */
>          VMSTATE_UINT32(xirr, ICPState),
> @@ -192,6 +216,7 @@ static TypeInfo icp_info = {
>      .parent = TYPE_DEVICE,
>      .instance_size = sizeof(ICPState),
>      .class_init = icp_class_init,
> +    .class_size = sizeof(ICPStateClass),
>  };
>  
>  /*
> @@ -353,10 +378,9 @@ static void ics_reset(DeviceState *dev)
>      }
>  }
>  
> -static int ics_post_load(void *opaque, int version_id)
> +static int ics_post_load(ICSState *ics)
>  {
>      int i;
> -    ICSState *ics = opaque;
>  
>      for (i = 0; i < ics->icp->nr_servers; i++) {
>          icp_resend(ics->icp, i);
> @@ -365,6 +389,28 @@ static int ics_post_load(void *opaque, int version_id)
>      return 0;
>  }
>  
> +static void ics_dispatch_pre_save(void *opaque)
> +{
> +    ICSState *ics = opaque;
> +    ICSStateClass *info = ICS_GET_CLASS(ics);
> +
> +    if (info->pre_save) {
> +        info->pre_save(ics);
> +    }
> +}
> +
> +static int ics_dispatch_post_load(void *opaque, int version_id)
> +{
> +    ICSState *ics = opaque;
> +    ICSStateClass *info = ICS_GET_CLASS(ics);
> +
> +    if (info->post_load) {
> +        return info->post_load(ics);

Pass version_id through?

> +    }
> +
> +    return 0;
> +}
> +
>  static const VMStateDescription vmstate_ics_irq = {
>      .name = "ics/irq",
>      .version_id = 1,
> @@ -384,7 +430,8 @@ static const VMStateDescription vmstate_ics = {
>      .version_id = 1,
>      .minimum_version_id = 1,
>      .minimum_version_id_old = 1,
> -    .post_load = ics_post_load,
> +    .pre_save = ics_dispatch_pre_save,
> +    .post_load = ics_dispatch_post_load,
>      .fields      = (VMStateField []) {
>          /* Sanity check */
>          VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
> @@ -409,10 +456,12 @@ static int ics_realize(DeviceState *dev)
>  static void ics_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> +    ICSStateClass *k = ICS_CLASS(klass);

isc?

Otherwise looks fine.

Andreas

>  
>      dc->init = ics_realize;
>      dc->vmsd = &vmstate_ics;
>      dc->reset = ics_reset;
> +    k->post_load = ics_post_load;
>  }
>  
>  static TypeInfo ics_info = {
> @@ -420,6 +469,7 @@ static TypeInfo ics_info = {
>      .parent = TYPE_DEVICE,
>      .instance_size = sizeof(ICSState),
>      .class_init = ics_class_init,
> +    .class_size = sizeof(ICSStateClass),
>  };
>  
>  /*
> @@ -612,7 +662,7 @@ static void xics_reset(DeviceState *d)
>      device_reset(DEVICE(icp->ics));
>  }
>  
> -void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
> +static void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
>  {
>      CPUState *cs = CPU(cpu);
>      CPUPPCState *env = &cpu->env;
> @@ -674,10 +724,12 @@ static Property xics_properties[] = {
>  static void xics_class_init(ObjectClass *oc, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
> +    XICSStateClass *k = XICS_CLASS(oc);
>  
>      dc->realize = xics_realize;
>      dc->props = xics_properties;
>      dc->reset = xics_reset;
> +    k->cpu_setup = xics_cpu_setup;
>  
>      spapr_rtas_register("ibm,set-xive", rtas_set_xive);
>      spapr_rtas_register("ibm,get-xive", rtas_get_xive);
> @@ -694,6 +746,7 @@ static const TypeInfo xics_info = {
>      .name          = TYPE_XICS,
>      .parent        = TYPE_SYS_BUS_DEVICE,
>      .instance_size = sizeof(XICSState),
> +    .class_size = sizeof(XICSStateClass),
>      .class_init    = xics_class_init,
>      .instance_init = xics_initfn,
>  };
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 16bfab9..432f0d2 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1155,8 +1155,6 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
>          }
>          env = &cpu->env;
>  
> -        xics_cpu_setup(spapr->icp, cpu);
> -
>          /* Set time-base frequency to 512 MHz */
>          cpu_ppc_tb_init(env, TIMEBASE_FREQ);
>  
> @@ -1170,6 +1168,8 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
>              kvmppc_set_papr(cpu);
>          }
>  
> +        xics_dispatch_cpu_setup(spapr->icp, cpu);
> +
>          qemu_register_reset(spapr_cpu_reset, cpu);
>      }
>  
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 66364c5..90ecaf8 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -32,6 +32,11 @@
>  #define TYPE_XICS "xics"
>  #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
>  
> +#define XICS_CLASS(klass) \
> +     OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS)
> +#define XICS_GET_CLASS(obj) \
> +     OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS)
> +
>  #define XICS_IPI        0x2
>  #define XICS_BUID       0x1
>  #define XICS_IRQ_BASE   (XICS_BUID << 12)
> @@ -41,11 +46,20 @@
>   * (the kernel implementation supports more but we don't exploit
>   *  that yet)
>   */
> +typedef struct XICSStateClass XICSStateClass;
>  typedef struct XICSState XICSState;
> +typedef struct ICPStateClass ICPStateClass;
>  typedef struct ICPState ICPState;
> +typedef struct ICSStateClass ICSStateClass;
>  typedef struct ICSState ICSState;
>  typedef struct ICSIRQState ICSIRQState;
>  
> +struct XICSStateClass {
> +    DeviceClass parent_class;
> +
> +    void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu);
> +};
> +
>  struct XICSState {
>      /*< private >*/
>      SysBusDevice parent_obj;
> @@ -59,6 +73,18 @@ struct XICSState {
>  #define TYPE_ICP "icp"
>  #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
>  
> +#define ICP_CLASS(klass) \
> +     OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
> +#define ICP_GET_CLASS(obj) \
> +     OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
> +
> +struct ICPStateClass {
> +    DeviceClass parent_class;
> +
> +    void (*pre_save)(ICPState *s);
> +    int (*post_load)(ICPState *s);
> +};
> +
>  struct ICPState {
>      /*< private >*/
>      DeviceState parent_obj;
> @@ -72,6 +98,18 @@ struct ICPState {
>  #define TYPE_ICS "ics"
>  #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
>  
> +#define ICS_CLASS(klass) \
> +     OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
> +#define ICS_GET_CLASS(obj) \
> +     OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
> +
> +struct ICSStateClass {
> +    DeviceClass parent_class;
> +
> +    void (*pre_save)(ICSState *s);
> +    int (*post_load)(ICSState *s);
> +};
> +
>  struct ICSState {
>      /*< private >*/
>      DeviceState parent_obj;
> @@ -98,6 +136,12 @@ struct ICSIRQState {
>  qemu_irq xics_get_qirq(XICSState *icp, int irq);
>  void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
>  
> -void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
> +static inline void xics_dispatch_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
> +{
> +    XICSStateClass *info = XICS_GET_CLASS(icp);
> +
> +    assert(info->cpu_setup);
> +    info->cpu_setup(icp, cpu);
> +}
>  
>  #endif /* __XICS_H__ */
>