From patchwork Tue Aug 6 08:27:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 264905 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C3DE92C0085 for ; Tue, 6 Aug 2013 18:29:07 +1000 (EST) Received: from localhost ([::1]:36157 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6cdc-0008S9-CI for incoming@patchwork.ozlabs.org; Tue, 06 Aug 2013 04:29:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6cct-0008Fw-UX for qemu-devel@nongnu.org; Tue, 06 Aug 2013 04:28:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6ccn-0003hl-ML for qemu-devel@nongnu.org; Tue, 06 Aug 2013 04:28:19 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:42218) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6ccn-0003hU-Af for qemu-devel@nongnu.org; Tue, 06 Aug 2013 04:28:13 -0400 Received: by mail-pa0-f49.google.com with SMTP id bi5so422431pad.22 for ; Tue, 06 Aug 2013 01:28:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eAp6qCuFiTdLn/FB2aLHEmqkRci6FgrUHpmXZQcxO6g=; b=bzgZnfWb71J6dXJ59vWtImEAvP2H7cn4oe8Zg2y2xcCLVU15GtD0kD2O1vSwg6kSk/ zPk9bkqxN/QF8QNx6cD3OCr5EL7Xn1/QV7Foo1Qkqe+YUatnK3VJls1MJHVMPrOcvfR9 Cj+NYywWnGVwuvFEj8zQCqo4xU7wteMhCoESaFB6xkTwsi82xQlUi8WLns8hK9aNwCE/ +8IiSeJN2tvrz18fGPGGmAUzjtqvdPfa2rYq4wXAyXm131URE1/GLM24LLmRJjbuHozI WleX3eOv7pv+Ln5KwUpxKvb7qElFf6DQ7b8QSu6mwNqyCJO7H5jazmAWXGvxK1yHG+/W Rc7Q== X-Gm-Message-State: ALoCoQnT4VQKIuGNhcC4ca4QcJlIY95fslNvKBYWhVEJcwMtdui796nKLuoErUgWEVZczorBYHCn X-Received: by 10.66.186.12 with SMTP id fg12mr1818784pac.178.1375777692568; Tue, 06 Aug 2013 01:28:12 -0700 (PDT) Received: from ka1.ozlabs.ibm.com (ibmaus65.lnk.telstra.net. [165.228.126.9]) by mx.google.com with ESMTPSA id qv4sm574174pbc.16.2013.08.06.01.28.07 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 06 Aug 2013 01:28:11 -0700 (PDT) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Tue, 6 Aug 2013 18:27:49 +1000 Message-Id: <1375777673-20274-3-git-send-email-aik@ozlabs.ru> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1375777673-20274-1-git-send-email-aik@ozlabs.ru> References: <1375777673-20274-1-git-send-email-aik@ozlabs.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.49 Cc: Anthony Liguori , Alexey Kardashevskiy , Alexander Graf , qemu-ppc@nongnu.org, Paul Mackerras , =?UTF-8?q?Andreas=20F=C3=A4rber?= , David Gibson Subject: [Qemu-devel] [PATCH 2/6] xics: add pre_save/post_load/cpu_setup dispatchers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The upcoming support of in-kernel XICS will redefine migration callbacks for both ICS and ICP so classes and callback pointers are added. This adds a cpu_setup callback to the XICS device class (as XICS-KVM will do it different) and xics_dispatch_cpu_setup(). This also moves the place where xics_dispatch_cpu_setup() is called a bit further to have VCPU initialized (required for XICS-KVM). Signed-off-by: Alexey Kardashevskiy --- hw/intc/xics.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++---- hw/ppc/spapr.c | 4 ++-- include/hw/ppc/xics.h | 46 +++++++++++++++++++++++++++++++++++++- 3 files changed, 104 insertions(+), 7 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 6b3c071..c5dad2f 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -153,11 +153,35 @@ static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority) } } +static void icp_dispatch_pre_save(void *opaque) +{ + ICPState *ss = opaque; + ICPStateClass *info = ICP_GET_CLASS(ss); + + if (info->pre_save) { + info->pre_save(ss); + } +} + +static int icp_dispatch_post_load(void *opaque, int version_id) +{ + ICPState *ss = opaque; + ICPStateClass *info = ICP_GET_CLASS(ss); + + if (info->post_load) { + return info->post_load(ss); + } + + return 0; +} + static const VMStateDescription vmstate_icp_server = { .name = "icp/server", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, + .pre_save = icp_dispatch_pre_save, + .post_load = icp_dispatch_post_load, .fields = (VMStateField []) { /* Sanity check */ VMSTATE_UINT32(xirr, ICPState), @@ -192,6 +216,7 @@ static TypeInfo icp_info = { .parent = TYPE_DEVICE, .instance_size = sizeof(ICPState), .class_init = icp_class_init, + .class_size = sizeof(ICPStateClass), }; /* @@ -353,10 +378,9 @@ static void ics_reset(DeviceState *dev) } } -static int ics_post_load(void *opaque, int version_id) +static int ics_post_load(ICSState *ics) { int i; - ICSState *ics = opaque; for (i = 0; i < ics->icp->nr_servers; i++) { icp_resend(ics->icp, i); @@ -365,6 +389,28 @@ static int ics_post_load(void *opaque, int version_id) return 0; } +static void ics_dispatch_pre_save(void *opaque) +{ + ICSState *ics = opaque; + ICSStateClass *info = ICS_GET_CLASS(ics); + + if (info->pre_save) { + info->pre_save(ics); + } +} + +static int ics_dispatch_post_load(void *opaque, int version_id) +{ + ICSState *ics = opaque; + ICSStateClass *info = ICS_GET_CLASS(ics); + + if (info->post_load) { + return info->post_load(ics); + } + + return 0; +} + static const VMStateDescription vmstate_ics_irq = { .name = "ics/irq", .version_id = 1, @@ -384,7 +430,8 @@ static const VMStateDescription vmstate_ics = { .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, - .post_load = ics_post_load, + .pre_save = ics_dispatch_pre_save, + .post_load = ics_dispatch_post_load, .fields = (VMStateField []) { /* Sanity check */ VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), @@ -409,10 +456,12 @@ static int ics_realize(DeviceState *dev) static void ics_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ICSStateClass *k = ICS_CLASS(klass); dc->init = ics_realize; dc->vmsd = &vmstate_ics; dc->reset = ics_reset; + k->post_load = ics_post_load; } static TypeInfo ics_info = { @@ -420,6 +469,7 @@ static TypeInfo ics_info = { .parent = TYPE_DEVICE, .instance_size = sizeof(ICSState), .class_init = ics_class_init, + .class_size = sizeof(ICSStateClass), }; /* @@ -612,7 +662,7 @@ static void xics_reset(DeviceState *d) device_reset(DEVICE(icp->ics)); } -void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) +static void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -674,10 +724,12 @@ static Property xics_properties[] = { static void xics_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + XICSStateClass *k = XICS_CLASS(oc); dc->realize = xics_realize; dc->props = xics_properties; dc->reset = xics_reset; + k->cpu_setup = xics_cpu_setup; spapr_rtas_register("ibm,set-xive", rtas_set_xive); spapr_rtas_register("ibm,get-xive", rtas_get_xive); @@ -694,6 +746,7 @@ static const TypeInfo xics_info = { .name = TYPE_XICS, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(XICSState), + .class_size = sizeof(XICSStateClass), .class_init = xics_class_init, .instance_init = xics_initfn, }; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 16bfab9..432f0d2 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1155,8 +1155,6 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) } env = &cpu->env; - xics_cpu_setup(spapr->icp, cpu); - /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, TIMEBASE_FREQ); @@ -1170,6 +1168,8 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) kvmppc_set_papr(cpu); } + xics_dispatch_cpu_setup(spapr->icp, cpu); + qemu_register_reset(spapr_cpu_reset, cpu); } diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 66364c5..90ecaf8 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -32,6 +32,11 @@ #define TYPE_XICS "xics" #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) +#define XICS_CLASS(klass) \ + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS) +#define XICS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS) + #define XICS_IPI 0x2 #define XICS_BUID 0x1 #define XICS_IRQ_BASE (XICS_BUID << 12) @@ -41,11 +46,20 @@ * (the kernel implementation supports more but we don't exploit * that yet) */ +typedef struct XICSStateClass XICSStateClass; typedef struct XICSState XICSState; +typedef struct ICPStateClass ICPStateClass; typedef struct ICPState ICPState; +typedef struct ICSStateClass ICSStateClass; typedef struct ICSState ICSState; typedef struct ICSIRQState ICSIRQState; +struct XICSStateClass { + DeviceClass parent_class; + + void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu); +}; + struct XICSState { /*< private >*/ SysBusDevice parent_obj; @@ -59,6 +73,18 @@ struct XICSState { #define TYPE_ICP "icp" #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) +#define ICP_CLASS(klass) \ + OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) +#define ICP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) + +struct ICPStateClass { + DeviceClass parent_class; + + void (*pre_save)(ICPState *s); + int (*post_load)(ICPState *s); +}; + struct ICPState { /*< private >*/ DeviceState parent_obj; @@ -72,6 +98,18 @@ struct ICPState { #define TYPE_ICS "ics" #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) +#define ICS_CLASS(klass) \ + OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) +#define ICS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS) + +struct ICSStateClass { + DeviceClass parent_class; + + void (*pre_save)(ICSState *s); + int (*post_load)(ICSState *s); +}; + struct ICSState { /*< private >*/ DeviceState parent_obj; @@ -98,6 +136,12 @@ struct ICSIRQState { qemu_irq xics_get_qirq(XICSState *icp, int irq); void xics_set_irq_type(XICSState *icp, int irq, bool lsi); -void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); +static inline void xics_dispatch_cpu_setup(XICSState *icp, PowerPCCPU *cpu) +{ + XICSStateClass *info = XICS_GET_CLASS(icp); + + assert(info->cpu_setup); + info->cpu_setup(icp, cpu); +} #endif /* __XICS_H__ */