[U-Boot,08/10] MIPS: mips32/cache.S: save return address in t9 register

Message ID 1371121176-20256-9-git-send-email-juhosg@openwrt.org
State Accepted
Delegated to: Daniel Schwierzeck
Headers show

Commit Message

Gabor Juhos June 13, 2013, 10:59 a.m.
Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
 arch/mips/cpu/mips32/cache.S |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 8158ea8..6d31909 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -34,7 +34,7 @@ 
-#define RA		t8
+#define RA		t9
  * 16kB is the maximum size of instruction and data caches on MIPS 4K,