drm/i915: Use the correct size of the GTT for placing the per-process entries

Submitted by Chris J Arges on April 24, 2013, 7:01 p.m.


Message ID 1366830066-16705-2-git-send-email-chris.j.arges@canonical.com
State New
Headers show

Commit Message

Chris J Arges April 24, 2013, 7:01 p.m.
From: Chris Wilson <chris@chris-wilson.co.uk>

The current layout is to place the per-process tables at the end of the
GTT. However, this is currently using a hardcoded maximum size for the GTT
and not taking in account limitations imposed by the BIOS. Use the value
for the total number of entries allocated in the table as provided by
the configuration registers.

Reported-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Matthew Garret <mjg@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 9a0f938bde74bf9e50bd75c8de9e38c1787398cd)

Signed-off-by: Chris J Arges <chris.j.arges@canonical.com>
Cc: stable@vger.kernel.org
 drivers/gpu/drm/i915/i915_gem_gtt.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eae804d..8096d577 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -72,7 +72,7 @@  int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 	/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 	 * entries. For aliasing ppgtt support we just steal them at the end for
 	 * now. */
-	first_pd_entry_in_global_pt = 512*1024 - I915_PPGTT_PD_ENTRIES;
+	first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
 	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 	if (!ppgtt)