Patchwork [v6,17/20] tcg-arm: Delete the 'S' constraint

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Submitter Richard Henderson
Date April 23, 2013, 8:46 p.m.
Message ID <1366750012-25015-18-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/239008/
State New
Headers show

Comments

Richard Henderson - April 23, 2013, 8:46 p.m.
After the previous patch, 's' and 'S' are the same.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)
Aurelien Jarno - April 24, 2013, 7:43 a.m.
On Tue, Apr 23, 2013 at 01:46:49PM -0700, Richard Henderson wrote:
> After the previous patch, 's' and 'S' are the same.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/arm/tcg-target.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 375c1e1..5fa3cb1 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -201,8 +201,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
>  
>      /* qemu_st address & data_reg */
>      case 's':
> -    /* qemu_st64 data_reg2 */
> -    case 'S':
>          ct->ct |= TCG_CT_REG;
>          tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
>          /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
> @@ -1928,7 +1926,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
>      { INDEX_op_qemu_st8, { "s", "s" } },
>      { INDEX_op_qemu_st16, { "s", "s" } },
>      { INDEX_op_qemu_st32, { "s", "s" } },
> -    { INDEX_op_qemu_st64, { "S", "S", "s" } },
> +    { INDEX_op_qemu_st64, { "s", "s", "s" } },
>  #else
>      { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
>      { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
> @@ -1940,7 +1938,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
>      { INDEX_op_qemu_st8, { "s", "s", "s" } },
>      { INDEX_op_qemu_st16, { "s", "s", "s" } },
>      { INDEX_op_qemu_st32, { "s", "s", "s" } },
> -    { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
> +    { INDEX_op_qemu_st64, { "s", "s", "s", "s" } },
>  #endif
>  
>      { INDEX_op_bswap16_i32, { "r", "r" } },

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

Patch

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 375c1e1..5fa3cb1 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -201,8 +201,6 @@  static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 
     /* qemu_st address & data_reg */
     case 's':
-    /* qemu_st64 data_reg2 */
-    case 'S':
         ct->ct |= TCG_CT_REG;
         tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
         /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
@@ -1928,7 +1926,7 @@  static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_qemu_st8, { "s", "s" } },
     { INDEX_op_qemu_st16, { "s", "s" } },
     { INDEX_op_qemu_st32, { "s", "s" } },
-    { INDEX_op_qemu_st64, { "S", "S", "s" } },
+    { INDEX_op_qemu_st64, { "s", "s", "s" } },
 #else
     { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
     { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
@@ -1940,7 +1938,7 @@  static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_qemu_st8, { "s", "s", "s" } },
     { INDEX_op_qemu_st16, { "s", "s", "s" } },
     { INDEX_op_qemu_st32, { "s", "s", "s" } },
-    { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
+    { INDEX_op_qemu_st64, { "s", "s", "s", "s" } },
 #endif
 
     { INDEX_op_bswap16_i32, { "r", "r" } },