From patchwork Tue Apr 23 20:46:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 239008 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 99DE02C0121 for ; Wed, 24 Apr 2013 06:56:35 +1000 (EST) Received: from localhost ([::1]:58908 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUkGP-0005RQ-8O for incoming@patchwork.ozlabs.org; Tue, 23 Apr 2013 16:56:33 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48854) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7i-000286-7G for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UUk7f-0003pS-FJ for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:34 -0400 Received: from mail-wi0-x230.google.com ([2a00:1450:400c:c05::230]:56093) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UUk7f-0003p9-8B for qemu-devel@nongnu.org; Tue, 23 Apr 2013 16:47:31 -0400 Received: by mail-wi0-f176.google.com with SMTP id hj19so6629288wib.3 for ; Tue, 23 Apr 2013 13:47:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=yk27g6pEd9fRiS4JfrbhlBk9lVE2A5FNYr63G/1a4X8=; b=BlzzXpNhEIlwTi8HOYLwi/viJ9PziHxdVwuqOwMoKCd6eQeZbBfFLVr8EVNytCEa6F H53srNli8ACNEi7tKDT7RSK2hG1mSSXhf4uC74Vh0Uzz2C+ZQxL1YYIqVWkpq2BWSBuS qDO/YZdYzdP0x9MqUI8t7Aj6UsjF0GbsRwrp3zAG9qPjTGySn5xMUj6xJ/6njLuOzG+j 25YA4Wza3hP/g8h0IqWRe9zri+WD8wZrV/qPMmcxATXbWmavW2VgYasuV5GQDQ005O/h AMJm2H6AH6ov+z1db7azErNVS9t8PQamxKvowUno1pNZi4f0Cq7YJISa4sJsdyvLxBgF x6XQ== X-Received: by 10.194.242.163 with SMTP id wr3mr63790514wjc.35.1366750050491; Tue, 23 Apr 2013 13:47:30 -0700 (PDT) Received: from fremont.twiddle.net ([212.183.132.78]) by mx.google.com with ESMTPS id q20sm18463501wiv.7.2013.04.23.13.47.29 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 23 Apr 2013 13:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2013 13:46:49 -0700 Message-Id: <1366750012-25015-18-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1366750012-25015-1-git-send-email-rth@twiddle.net> References: <1366750012-25015-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c05::230 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v6 17/20] tcg-arm: Delete the 'S' constraint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org After the previous patch, 's' and 'S' are the same. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 375c1e1..5fa3cb1 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -201,8 +201,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) /* qemu_st address & data_reg */ case 's': - /* qemu_st64 data_reg2 */ - case 'S': ct->ct |= TCG_CT_REG; tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) @@ -1928,7 +1926,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_qemu_st8, { "s", "s" } }, { INDEX_op_qemu_st16, { "s", "s" } }, { INDEX_op_qemu_st32, { "s", "s" } }, - { INDEX_op_qemu_st64, { "S", "S", "s" } }, + { INDEX_op_qemu_st64, { "s", "s", "s" } }, #else { INDEX_op_qemu_ld8u, { "r", "l", "l" } }, { INDEX_op_qemu_ld8s, { "r", "l", "l" } }, @@ -1940,7 +1938,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_qemu_st8, { "s", "s", "s" } }, { INDEX_op_qemu_st16, { "s", "s", "s" } }, { INDEX_op_qemu_st32, { "s", "s", "s" } }, - { INDEX_op_qemu_st64, { "S", "S", "s", "s" } }, + { INDEX_op_qemu_st64, { "s", "s", "s", "s" } }, #endif { INDEX_op_bswap16_i32, { "r", "r" } },