Patchwork [arm-devs,v1,03/15] xilinx_spips: Inhibit interrupts in LQSPI mode

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Submitter Peter Crosthwaite
Date April 3, 2013, 4:27 a.m.
Message ID <a227467fd866281a89e1fa73e830a0f5f38438cc.1364962908.git.peter.crosthwaite@xilinx.com>
Download mbox | patch
Permalink /patch/233221/
State New
Headers show

Comments

Peter Crosthwaite - April 3, 2013, 4:27 a.m.
The real hardware does not produce interrupts in LQSPI mode. Inhibit
generation of interrupts when the LQ_MODE bit is set.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/xilinx_spips.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)
Peter Maydell - April 5, 2013, 6:41 p.m.
On 3 April 2013 05:27, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote:
> The real hardware does not produce interrupts in LQSPI mode. Inhibit
> generation of interrupts when the LQ_MODE bit is set.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
>
>  hw/xilinx_spips.c |    7 ++++++-
>  1 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
> index 261d948..a8691d5 100644
> --- a/hw/xilinx_spips.c
> +++ b/hw/xilinx_spips.c
> @@ -204,6 +204,9 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
>
>  static void xilinx_spips_update_ixr(XilinxSPIPS *s)
>  {
> +    if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
> +        return;
> +    }
>      /* These are set/cleared as they occur */
>      s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
>                                  IXR_TX_FIFO_MODE_FAIL);
> @@ -256,7 +259,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
>          for (i = 0; i < num_effective_busses(s); ++i) {
>              if (!i || s->snoop_state == SNOOP_STRIPING) {
>                  if (fifo8_is_empty(&s->tx_fifo)) {
> -                    s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
> +                    if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
> +                        s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
> +                    }
>                      xilinx_spips_update_ixr(s);
>                      return;
>                  } else {

How about the OVERFLOW case just below here, or is that a
deliberate omission?

-- PMM
Peter Crosthwaite - April 7, 2013, 10:52 p.m.
Hi Peter,

On Sat, Apr 6, 2013 at 4:41 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 3 April 2013 05:27, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote:
>> The real hardware does not produce interrupts in LQSPI mode. Inhibit
>> generation of interrupts when the LQ_MODE bit is set.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> ---
>>
>>  hw/xilinx_spips.c |    7 ++++++-
>>  1 files changed, 6 insertions(+), 1 deletions(-)
>>
>> diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
>> index 261d948..a8691d5 100644
>> --- a/hw/xilinx_spips.c
>> +++ b/hw/xilinx_spips.c
>> @@ -204,6 +204,9 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
>>
>>  static void xilinx_spips_update_ixr(XilinxSPIPS *s)
>>  {
>> +    if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
>> +        return;
>> +    }
>>      /* These are set/cleared as they occur */
>>      s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
>>                                  IXR_TX_FIFO_MODE_FAIL);
>> @@ -256,7 +259,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
>>          for (i = 0; i < num_effective_busses(s); ++i) {
>>              if (!i || s->snoop_state == SNOOP_STRIPING) {
>>                  if (fifo8_is_empty(&s->tx_fifo)) {
>> -                    s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
>> +                    if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
>> +                        s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
>> +                    }
>>                      xilinx_spips_update_ixr(s);
>>                      return;
>>                  } else {
>
> How about the OVERFLOW case just below here, or is that a
> deliberate omission?
>

Deliberate omission. Overflow in LQPSI mode should be impossible as
LQSPI always resets the fifos and does one pop for every push. You
could make this happen if you tried to do non-linear accesses while in
linear mode but this is undefined behaviour (perhaps worthy of a
LOG_GUEST_ERROR on the register access but that's a separate followup
patch).

Regards,
Peter

> -- PMM
>

Patch

diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
index 261d948..a8691d5 100644
--- a/hw/xilinx_spips.c
+++ b/hw/xilinx_spips.c
@@ -204,6 +204,9 @@  static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 
 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 {
+    if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
+        return;
+    }
     /* These are set/cleared as they occur */
     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
                                 IXR_TX_FIFO_MODE_FAIL);
@@ -256,7 +259,9 @@  static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
         for (i = 0; i < num_effective_busses(s); ++i) {
             if (!i || s->snoop_state == SNOOP_STRIPING) {
                 if (fifo8_is_empty(&s->tx_fifo)) {
-                    s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
+                    if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
+                        s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
+                    }
                     xilinx_spips_update_ixr(s);
                     return;
                 } else {