diff mbox

[U-Boot] Tegra114: Fix/update GP padcfg register struct

Message ID 1363214098-30952-1-git-send-email-twarren@nvidia.com
State Superseded
Delegated to: Tom Warren
Headers show

Commit Message

Tom Warren March 13, 2013, 10:34 p.m. UTC 
Differences in padcfg registers (some removed, some added) between
Tegra30 and Tegra114 weren't picked up when I ported this file.
Also removed the HSM setting for SDIOCFG - not called out in TRM.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra114/gp_padctrl.h |   84 ++++++++++++++---------
 1 files changed, 51 insertions(+), 33 deletions(-)

Comments

Stephen Warren March 13, 2013, 11:30 p.m. UTC | #1 
On 03/13/2013 04:34 PM, Tom Warren wrote:
> Differences in padcfg registers (some removed, some added) between
> Tegra30 and Tegra114 weren't picked up when I ported this file.
> Also removed the HSM setting for SDIOCFG - not called out in TRM.

The actual diff would be a lot easier to see if the register offsets
hadn't all had 0x800 added to them as well in the same patch. MODEREG
and HIDREV are at the same absolute address in Tegra20/30/114 for example.

I didn't check the content of this patch due to that, but it seems fine
if it matches the TRM.
Stephen Warren March 14, 2013, 4:38 a.m. UTC | #2 
On 03/13/2013 08:13 PM, Tom Warren wrote:
> Stephen,
> 
>> -----Original Message-----
>> From: Stephen Warren [mailto:swarren@wwwdotorg.org]
>> Sent: Wednesday, March 13, 2013 4:30 PM
>> To: Tom Warren
>> Cc: u-boot@lists.denx.de; Stephen Warren; Tom Warren
>> Subject: Re: [U-Boot] [PATCH] Tegra114: Fix/update GP padcfg register struct
>>
>> On 03/13/2013 04:34 PM, Tom Warren wrote:
>>> Differences in padcfg registers (some removed, some added) between
>>> Tegra30 and Tegra114 weren't picked up when I ported this file.
>>> Also removed the HSM setting for SDIOCFG - not called out in TRM.
>>
>> The actual diff would be a lot easier to see if the register offsets hadn't all
>> had 0x800 added to them as well in the same patch. MODEREG and HIDREV
>> are at the same absolute address in Tegra20/30/114 for example.
> I felt it prudent to add 0x800 since the register addresses spilled over into the 0x900 range, and it would have looked weird to have 0xFC, then 0x900, 0x904, etc.
> I could revert the old offset, and then make the change to the new regs go 0xFC, then 0x100, 0x104, etc. i.e. offset based off of the absolute address of the GP base of 0x70000800. Let me know.

I think it'd make sense to either list the offsets as relative to the
start of the struct (as they are now), or have 2 separate patches the
first adding 0x800 to everything as a simple/obvious patch, and the
second fixing the struct to match Tegra114 HW.
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
index c538bdd..b2ba75f 100644
--- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
@@ -21,39 +21,57 @@ 
 
 /* APB_MISC_GP and padctrl registers */
 struct apb_misc_gp_ctlr {
-	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
-	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
-	u32	reserved0[22];	/* 0x08 - 0x5C: */
-	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
-	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
-	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
-	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
-	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
-	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
-	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
-	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
-	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
-	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
-	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
-	u32	csuscfg;	/* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
-	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
-	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
-	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
-	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
-	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
-	u32	lcdcfg1;	/* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
-	u32	lcdcfg2;	/* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
-	u32	sdio2cfg;	/* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
-	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
-	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
-	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
-	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
-	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
-	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
-	u32	vicfg1;		/* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
-	u32	vivttgen;	/* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
-	u32	reserved1[7];	/* 0xD0-0xE8: */
-	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	modereg;	/* 0x800: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x804: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x808 - 0x85C: */
+	u32	emu_revid;	/* 0x860: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x864: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x868: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x86C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x870: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x874: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x878: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x87C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x880: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x884: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x888: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x88C: */
+	u32	dap1cfg;	/* 0x890: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x894: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x898: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x89C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0x8A0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0x8A4 - 0x8AC: */
+	u32	sdio3cfg;	/* 0x8B0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0x8B4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0x8B8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0x8BC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0x8C0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0x8C4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0x8C8-0x8E8: */
+	u32	sdio1cfg;	/* 0x8EC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0x8F0-0x8F8: */
+	u32	ddccfg;		/* 0x8FC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x900: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x904-0x90C: */
+	u32	gmecfg;		/* 0x910: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x914: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x918: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x91C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x920: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x924: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x928: */
+	u32	dev3cfg;	/* 0x92C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x930 - 0x934: */
+	u32	ceccfg;		/* 0x938: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[20];	/* 0x93C - 0x990: */
+	u32	atcfg6;		/* 0x994: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x998: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x99C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x9A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x9A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x9A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x9AC: APB_MISC_GP_AOCFG0PADCTRL */
 };
 
 #endif	/* _TEGRA114_GP_PADCTRL_H_ */