| Message ID | 1347482678-9458-3-git-send-email-sw@weilnetz.de |
|---|---|
| State | Superseded |
| Headers | show |
On 12 September 2012 21:44, Stefan Weil <sw@weilnetz.de> wrote: > --- a/tcg/i386/tcg-target.c > +++ b/tcg/i386/tcg-target.c > @@ -75,9 +75,7 @@ static const int tcg_target_call_iarg_regs[] = { > TCG_REG_R8, > TCG_REG_R9, > #else > - TCG_REG_EAX, > - TCG_REG_EDX, > - TCG_REG_ECX > + /* 32 bit mode uses stack based calling convention (GCC default). */ > #endif > }; This makes the array zero-length for 32 bit targets, but functions like tcg_out_tlb_load() and tcg_out_qemu_ld() still unconditionally access elements in it... -- PMM
Am 12.09.2012 23:18, schrieb Peter Maydell: > On 12 September 2012 21:44, Stefan Weil <sw@weilnetz.de> wrote: >> --- a/tcg/i386/tcg-target.c >> +++ b/tcg/i386/tcg-target.c >> @@ -75,9 +75,7 @@ static const int tcg_target_call_iarg_regs[] = { >> TCG_REG_R8, >> TCG_REG_R9, >> #else >> - TCG_REG_EAX, >> - TCG_REG_EDX, >> - TCG_REG_ECX >> + /* 32 bit mode uses stack based calling convention (GCC default). */ >> #endif >> }; > This makes the array zero-length for 32 bit targets, but functions > like tcg_out_tlb_load() and tcg_out_qemu_ld() still unconditionally > access elements in it... > > -- PMM Thanks for the hint. I'm afraid there are a lot more functions of that kind in i386/tcg-target.c. I could use conditional compilation for those accesses, but first I'd like to understand why this works at all. - sw
On 09/12/2012 10:50 PM, Stefan Weil wrote: > I could use conditional compilation for those accesses, > but first I'd like to understand why this works at all. Before your patch you mean? Because those are the registers reserved by the "L" constraint. r~
On 13 September 2012 06:50, Stefan Weil <sw@weilnetz.de> wrote: > Am 12.09.2012 23:18, schrieb Peter Maydell: >> This makes the array zero-length for 32 bit targets, but functions >> like tcg_out_tlb_load() and tcg_out_qemu_ld() still unconditionally >> access elements in it... > Thanks for the hint. I'm afraid there are a lot more functions > of that kind in i386/tcg-target.c. > > I could use conditional compilation for those accesses, > but first I'd like to understand why this works at all. The functions in question are generating code that needs to use some temporary registers. (As RTH says, this lines up with the L constraint marking those registers as not usable for the relevant TCG operands.) To avoid unnecessary register copies in the old pre-commit-6a18ae2d register-based calling convention, they are forcing those temporary registers to be the same as some of the registers that were used for function arguments. Now we no longer use a register-based calling convention it doesn't matter which registers we use as long as the functions and the constraint definitions match up. The only tricky bit will be that the 64-bit-target cases do still care about using the same registers as are used for function inputs. -- PMM
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 43b5572..d60bab8 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -75,9 +75,7 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R8, TCG_REG_R9, #else - TCG_REG_EAX, - TCG_REG_EDX, - TCG_REG_ECX + /* 32 bit mode uses stack based calling convention (GCC default). */ #endif }; @@ -117,11 +115,7 @@ static void patch_reloc(uint8_t *code_ptr, int type, /* maximum number of register used for input function arguments */ static inline int tcg_target_get_call_iarg_regs_count(int flags) { - if (TCG_TARGET_REG_BITS == 64) { - return ARRAY_SIZE(tcg_target_call_iarg_regs); - } - - return 0; + return ARRAY_SIZE(tcg_target_call_iarg_regs); } /* parse target specific constraints */
32 bit x86 hosts don't need registers for helper function arguments because they use the default stack based calling convention. Removing the registers allows simpler code for function tcg_target_get_call_iarg_regs_count. Signed-off-by: Stefan Weil <sw@weilnetz.de> --- tcg/i386/tcg-target.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-)