| Message ID | 1347154198-8629-8-git-send-email-jcmvbkbc@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 9 September 2012 02:29, Max Filippov <jcmvbkbc@gmail.com> wrote: > +uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) > +{ > + float_status fp_status = {0}; > + float32 zero = {0}; This probably won't compile if you turn on USE_SOFTFLOAT_STRUCT_TYPES in softfloat.h. (That's a define intended to assist in avoiding accidental mixing of the softfloat types with native int/float types.) In any case softfloat.h provides a float32_zero which is probably what you want to use here. > + float32 res; > + > + set_float_rounding_mode(rounding_mode, &fp_status); > + > + res = float32_mul(v, uint32_to_float32(scale, &fp_status), &fp_status); Can you use the softflota scalbn function here instead? > + > + if (float32_compare_quiet(v, zero, &fp_status) == float_relation_less) { > + return float32_to_int32(res, &fp_status); > + } else { > + return float32_to_uint32(res, &fp_status); > + } This looks rather odd...are you sure it's correct? > +} > + > +float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) > +{ > + return float32_div( > + int32_to_float32(v, &env->fp_status), > + uint32_to_float32(scale, &env->fp_status), > + &env->fp_status); > +} > + > +float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) > +{ > + return float32_div( > + uint32_to_float32(v, &env->fp_status), > + uint32_to_float32(scale, &env->fp_status), > + &env->fp_status); Again, scalbn should let you avoid this division. (check how the ARM float-to-int and int-to-float are done, I think the semantics are similar.) -- PMM
On Sun, Sep 9, 2012 at 3:06 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > On 9 September 2012 02:29, Max Filippov <jcmvbkbc@gmail.com> wrote: >> +uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) >> +{ >> + float_status fp_status = {0}; >> + float32 zero = {0}; > > This probably won't compile if you turn on USE_SOFTFLOAT_STRUCT_TYPES It will, but thanks for the hint, gdbstub breaks with this macro defined. > in softfloat.h. (That's a define intended to assist in avoiding > accidental mixing of the softfloat types with native int/float types.) > > In any case softfloat.h provides a float32_zero which is probably what > you want to use here. > >> + float32 res; >> + >> + set_float_rounding_mode(rounding_mode, &fp_status); >> + >> + res = float32_mul(v, uint32_to_float32(scale, &fp_status), &fp_status); > > Can you use the softflota scalbn function here instead? Sure, had to search for it harder myself... >> + >> + if (float32_compare_quiet(v, zero, &fp_status) == float_relation_less) { >> + return float32_to_int32(res, &fp_status); >> + } else { >> + return float32_to_uint32(res, &fp_status); >> + } > > This looks rather odd...are you sure it's correct? Unfortunately this is what Tensilica ISS does. Doesn't match what ISA specifies and both are a bit counter-intuitive. I've mailed a question to Tensilica guys, will see what they answer.
diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h index 4e6e417..9557347 100644 --- a/target-xtensa/helper.h +++ b/target-xtensa/helper.h @@ -44,5 +44,9 @@ DEF_HELPER_3(sub_s, f32, env, f32, f32) DEF_HELPER_3(mul_s, f32, env, f32, f32) DEF_HELPER_4(madd_s, f32, env, f32, f32, f32) DEF_HELPER_4(msub_s, f32, env, f32, f32, f32) +DEF_HELPER_FLAGS_3(ftoi, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32) +DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_CONST | TCG_CALL_PURE, i32, f32, i32, i32) +DEF_HELPER_3(itof, f32, env, i32, i32) +DEF_HELPER_3(uitof, f32, env, i32, i32) #include "def-helper.h" diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index ba935a8..d85f9d0 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -821,3 +821,46 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) return float32_muladd(b, c, a, float_muladd_negate_product, &env->fp_status); } + +uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = {0}; + + set_float_rounding_mode(rounding_mode, &fp_status); + return float32_to_int32( + float32_mul(v, uint32_to_float32(scale, &fp_status), &fp_status), + &fp_status); +} + +uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = {0}; + float32 zero = {0}; + float32 res; + + set_float_rounding_mode(rounding_mode, &fp_status); + + res = float32_mul(v, uint32_to_float32(scale, &fp_status), &fp_status); + + if (float32_compare_quiet(v, zero, &fp_status) == float_relation_less) { + return float32_to_int32(res, &fp_status); + } else { + return float32_to_uint32(res, &fp_status); + } +} + +float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_div( + int32_to_float32(v, &env->fp_status), + uint32_to_float32(scale, &env->fp_status), + &env->fp_status); +} + +float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_div( + uint32_to_float32(v, &env->fp_status), + uint32_to_float32(scale, &env->fp_status), + &env->fp_status); +} diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index ec22f60..a6ab18a 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1915,6 +1915,54 @@ static void disas_xtensa_insn(DisasContext *dc) cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); break; + case 8: /*ROUND.Sf*/ + case 9: /*TRUNC.Sf*/ + case 10: /*FLOOR.Sf*/ + case 11: /*CEIL.Sf*/ + case 14: /*UTRUNC.Sf*/ + gen_window_check1(dc, RRR_R); + { + static const unsigned rounding_mode_const[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_down, + float_round_up, + [6] = float_round_to_zero, + }; + TCGv_i32 rounding_mode = tcg_const_i32( + rounding_mode_const[OP2 & 7]); + TCGv_i32 scale = tcg_const_i32(1 << RRR_T); + + if (OP2 == 14) { + gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], + rounding_mode, scale); + } else { + gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], + rounding_mode, scale); + } + + tcg_temp_free(rounding_mode); + tcg_temp_free(scale); + } + break; + + case 12: /*FLOAT.Sf*/ + case 13: /*UFLOAT.Sf*/ + gen_window_check1(dc, RRR_S); + { + TCGv_i32 scale = tcg_const_i32(1 << RRR_T); + + if (OP2 == 13) { + gen_helper_uitof(cpu_FR[RRR_R], cpu_env, + cpu_R[RRR_S], scale); + } else { + gen_helper_itof(cpu_FR[RRR_R], cpu_env, + cpu_R[RRR_S], scale); + } + tcg_temp_free(scale); + } + break; + case 15: /*FP1OP*/ switch (RRR_T) { case 0: /*MOV.Sf*/
These are FP to integer and integer to FP conversion opcodes. See ISA, 4.3.10 for more details. Note that utrunc.s implementation follows ISS behaviour, not ISA. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> --- target-xtensa/helper.h | 4 +++ target-xtensa/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++++ target-xtensa/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+), 0 deletions(-)