[10/10] hw/cadence_gem: Make rx_desc_addr and tx_desc_addr uint32_t

Message ID 1341400454-20145-11-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell July 4, 2012, 11:14 a.m.
Make the state fields rx_desc_addr and tx_desc_addr uint32_t;
this matches the VMStateDescription, and also conforms to how
hardware works: the registers don't magically become larger
if the device is attached to a CPU with a larger physical
address size. It also fixes a compile failure if the
target_phys_addr_t type is changed to 64 bits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
 hw/cadence_gem.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
index dbde392..87143ca 100644
--- a/hw/cadence_gem.c
+++ b/hw/cadence_gem.c
@@ -339,8 +339,8 @@  typedef struct {
     uint8_t phy_loop; /* Are we in phy loopback? */
     /* The current DMA descriptor pointers */
-    target_phys_addr_t rx_desc_addr;
-    target_phys_addr_t tx_desc_addr;
+    uint32_t rx_desc_addr;
+    uint32_t tx_desc_addr;
 } GemState;