Message ID | 1336698455-11921-1-git-send-email-festevam@gmail.com |
---|---|
State | Superseded |
Delegated to: | Anatolij Gustschin |
Headers | show |
>-----Original Message----- >From: Fabio Estevam [mailto:festevam@gmail.com] >Sent: Friday, May 11, 2012 9:08 AM >To: u-boot@lists.denx.de >Cc: sbabic@denx.de; Liu Hui-R64343; Estevam Fabio-R49496 >Subject: [PATCH 1/3] mx53: Change IPU_CTRL_BASE_ADDR definition > >From: Fabio Estevam <fabio.estevam@freescale.com> > >The original definition of IPU_CTRL_BASE_ADDR does match the value stated >in the MX53 Reference Manual. > >However, if using such value the IPU driver hangs when trying to access the >IPU registers. > >Looking for this definition in Freescale U-boot version shows that it is set as 0. > >Set it as 0 here as well, so that we can have a working IPU driver for mx53. > >Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <r64343@freescale.com> >--- > arch/arm/include/asm/arch-mx5/imx-regs.h | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > >diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h >b/arch/arm/include/asm/arch-mx5/imx-regs.h >index cef4190..171c4ab 100644 >--- a/arch/arm/include/asm/arch-mx5/imx-regs.h >+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h >@@ -34,7 +34,7 @@ > #define NFC_BASE_ADDR_AXI 0xCFFF0000 > #define CS1_BASE_ADDR 0xB8000000 > #elif defined(CONFIG_MX53) >-#define IPU_CTRL_BASE_ADDR 0x18000000 >+#define IPU_CTRL_BASE_ADDR 0x00000000 > #define SPBA0_BASE_ADDR 0x50000000 > #define AIPS1_BASE_ADDR 0x53F00000 > #define AIPS2_BASE_ADDR 0x63F00000 >-- >1.7.1 >
On 11/05/2012 03:07, Fabio Estevam wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > The original definition of IPU_CTRL_BASE_ADDR does match the value stated > in the MX53 Reference Manual. > > However, if using such value the IPU driver hangs when trying to access the IPU registers. > > Looking for this definition in Freescale U-boot version shows that it is set as 0. > > Set it as 0 here as well, so that we can have a working IPU driver for mx53. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- Hi Fabio, > arch/arm/include/asm/arch-mx5/imx-regs.h | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h > index cef4190..171c4ab 100644 > --- a/arch/arm/include/asm/arch-mx5/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h > @@ -34,7 +34,7 @@ > #define NFC_BASE_ADDR_AXI 0xCFFF0000 > #define CS1_BASE_ADDR 0xB8000000 > #elif defined(CONFIG_MX53) > -#define IPU_CTRL_BASE_ADDR 0x18000000 > +#define IPU_CTRL_BASE_ADDR 0x00000000 > #define SPBA0_BASE_ADDR 0x50000000 > #define AIPS1_BASE_ADDR 0x53F00000 > #define AIPS2_BASE_ADDR 0x63F00000 Apart of the fact that it works, this chane appears really strange to me. Maybe now it is not writing anymore in ipu, and the default values are ok for mx53. It seems more a MX53 related issu in IPU3 driver, and this change maybe hides the real problem. Do you have any additional information to make this modification against the official Freescale's reference manual ? Regards, Stefano
Hi Stefano, On Fri, May 11, 2012 at 7:46 AM, Stefano Babic <sbabic@denx.de> wrote: > Apart of the fact that it works, this chane appears really strange to > me. Maybe now it is not writing anymore in ipu, and the default values > are ok for mx53. It seems more a MX53 related issu in IPU3 driver, and > this change maybe hides the real problem. Do you have any additional > information to make this modification against the official Freescale's > reference manual ? I investigated this and I understand it better now. I am working on a solution that will be flexible to handle mx51/mx53/mx6. Regards, Fabio Estevam
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index cef4190..171c4ab 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -34,7 +34,7 @@ #define NFC_BASE_ADDR_AXI 0xCFFF0000 #define CS1_BASE_ADDR 0xB8000000 #elif defined(CONFIG_MX53) -#define IPU_CTRL_BASE_ADDR 0x18000000 +#define IPU_CTRL_BASE_ADDR 0x00000000 #define SPBA0_BASE_ADDR 0x50000000 #define AIPS1_BASE_ADDR 0x53F00000 #define AIPS2_BASE_ADDR 0x63F00000