| Message ID | 1336445361-7762-1-git-send-email-mporter@ti.com |
|---|---|
| State | Accepted |
| Commit | a3c3fabb0f65455068e01197e16927f0589beaa2 |
| Delegated to: | Tom Rini |
| Headers | show |
On Mon, May 07, 2012 at 10:49:21PM -0400, Matt Porter wrote: > In warm reset conditions on OMAP36xx/AM/DM37xx the rom code > incorrectly sets the DPLL4 clock input divider to /6.5 which > is an invalid value unless the input clock is 13MHz. When a JTAG > emulator is attached, a warm reset is necessary after the emulator > gains control of the process. This results in a loss of serial > output due to the invalid DPLL4 settings. > > This patch fixes the issue by resetting the DPLL4 clock input > divider to /1 when the input clock is not 13MHz. AM/DM37x TRM > section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only > used when the input clock is 13MHz. > > Signed-off-by: Matt Porter <mporter@ti.com> Applied to u-boot-ti/master, thanks.
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 567817e..09c51f6 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -572,6 +572,22 @@ void prcm_init(void) } if (get_cpu_family() == CPU_OMAP36XX) { + /* + * In warm reset conditions on OMAP36xx/AM/DM37xx + * the rom code incorrectly sets the DPLL4 clock + * input divider to /6.5. Section 3.5.3.3.3.2.1 of + * the AM/DM37x TRM explains that the /6.5 divider + * is used only when the input clock is 13MHz. + * + * If the part is in this cpu family *and* the input + * clock *is not* 13 MHz, then reset the DPLL4 clock + * input divider to /1 as it should never set to /6.5 + * in this case. + */ + if (sys_clkin_sel != 1) /* 13 MHz */ + /* Bit 8: DPLL4_CLKINP_DIV */ + sr32(&prm_base->clksrc_ctrl, 8, 1, 0); + /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com> --- arch/arm/cpu/armv7/omap3/clock.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)