Patchwork [U-Boot,v2,3/5] msm7x30: Add support for msm7x30 SoC

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Submitter mohamed.haneef@lntinfotech.com
Date March 5, 2012, 2:39 p.m.
Message ID <1330958354-24649-1-git-send-email-mohamed.haneef@lntinfotech.com>
Download mbox | patch
Permalink /patch/144693/
State Changes Requested
Delegated to: Albert ARIBAUD
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mohamed.haneef@lntinfotech.com - March 5, 2012, 2:39 p.m.
* Support for Qualcomm msm7630 SoC

Signed-off-by: Mohamed Haneef <mohamed.haneef@lntinfotech.com>
---

Changes for v2:
 - removed BIT() macro and replacing with (3 << 6) in the macro VERG_CONFIG
 - removed the unwanted comment line
 - removed Intitalize the Watchpoint Controll Register to zero, since optional
 - removed reset_timer_masked function since it is not used any where


 arch/arm/cpu/armv7/msm7630/Makefile           |   59 +++
 arch/arm/cpu/armv7/msm7630/acpuclock.c        |  327 +++++++++++++
 arch/arm/cpu/armv7/msm7630/board.c            |   57 +++
 arch/arm/cpu/armv7/msm7630/config.mk          |    1 +
 arch/arm/cpu/armv7/msm7630/gpio.c             |  229 +++++++++
 arch/arm/cpu/armv7/msm7630/lowlevel_init.S    |  623 +++++++++++++++++++++++++
 arch/arm/cpu/armv7/msm7630/timer.c            |  142 ++++++
 arch/arm/include/asm/arch-msm7630/adm.h       |   28 ++
 arch/arm/include/asm/arch-msm7630/gpio.h      |   47 ++
 arch/arm/include/asm/arch-msm7630/gpio_hw.h   |  168 +++++++
 arch/arm/include/asm/arch-msm7630/iomap.h     |   96 ++++
 arch/arm/include/asm/arch-msm7630/proc_comm.h |   42 ++
 arch/arm/include/asm/arch-msm7630/sys_proto.h |   29 ++
 13 files changed, 1848 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/msm7630/Makefile
 create mode 100644 arch/arm/cpu/armv7/msm7630/acpuclock.c
 create mode 100644 arch/arm/cpu/armv7/msm7630/board.c
 create mode 100644 arch/arm/cpu/armv7/msm7630/config.mk
 create mode 100644 arch/arm/cpu/armv7/msm7630/gpio.c
 create mode 100644 arch/arm/cpu/armv7/msm7630/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/msm7630/timer.c
 create mode 100644 arch/arm/include/asm/arch-msm7630/adm.h
 create mode 100644 arch/arm/include/asm/arch-msm7630/gpio.h
 create mode 100644 arch/arm/include/asm/arch-msm7630/gpio_hw.h
 create mode 100644 arch/arm/include/asm/arch-msm7630/iomap.h
 create mode 100644 arch/arm/include/asm/arch-msm7630/proc_comm.h
 create mode 100644 arch/arm/include/asm/arch-msm7630/sys_proto.h

--
1.7.1


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Patch

diff --git a/arch/arm/cpu/armv7/msm7630/Makefile b/arch/arm/cpu/armv7/msm7630/Makefile
new file mode 100644
index 0000000..d9dfade
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/Makefile
@@ -0,0 +1,59 @@ 
+#
+# (C) Copyright 2012
+# LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# The AVP is ARMv4T architecture so we must use special compiler
+# flags for any startup files it might use.
+#CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t
+#CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t
+
+include $(TOPDIR)/config.mk
+
+LIB    =  $(obj)lib$(SOC).o
+
+SOBJS-y        := lowlevel_init.o
+COBJS-y                := board.o
+COBJS-y                += timer.o
+COBJS-y                += acpuclock.o
+COBJS-y                += gpio.o
+
+ SRCS  := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ OBJS  := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
+
+all:    $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/msm7630/acpuclock.c b/arch/arm/cpu/armv7/msm7630/acpuclock.c
new file mode 100644
index 0000000..73570fc
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/acpuclock.c
@@ -0,0 +1,327 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <asm/arch/iomap.h>
+#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/proc_comm.h>
+#define ACPU_806MHZ            42
+#define ACPU_1024MHZ           53
+#define ACPU_1200MHZ           125
+#define ACPU_1400MHZ           73
+
+/* Macros to select PLL2 with divide by 1 */
+#define ACPU_SRC_SEL           3
+#define ACPU_SRC_DIV           0
+
+#define VREG_CONFIG    (3 << 6)
+#define VREG_DATA      (VREG_CONFIG | (VREF_SEL << 5))
+#define VREF_SEL       1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */
+#define V_STEP         (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */
+#define MV(mv)         ((mv) / (!((mv) % V_STEP)))
+/* mv = (750mV + (raw * 25mV)) * (2 - VREF_SEL) */
+#define VDD_RAW(mv)    (((MV(mv) / V_STEP) - 30) | VREG_DATA)
+
+
+/* enum for SDC CLK IDs */
+enum {
+       SDC1_CLK  = 19,
+       SDC1_PCLK = 20,
+       SDC2_CLK  = 21,
+       SDC2_PCLK = 22,
+       SDC3_CLK  = 23,
+       SDC3_PCLK = 24,
+       SDC4_CLK  = 25,
+       SDC4_PCLK = 26
+};
+
+/* Zero'th entry is dummy */
+static uint8_t sdc_clk[]  = {0, SDC1_CLK,  SDC2_CLK,  SDC3_CLK,  SDC4_CLK};
+static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
+
+void spm_init(void)
+{
+       writel(0x05, MSM_SAW_BASE + 0x10); /* MSM_SPM_REG_SAW_CFG */
+       writel(0x18, MSM_SAW_BASE + 0x14); /* MSM_SPM_REG_SAW_SPM_CTL */
+       writel(0x00006666, MSM_SAW_BASE + 0x18);
+       /* MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY */
+       writel(0xFF000666, MSM_SAW_BASE + 0x1C);
+       /* MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY */
+       writel(0x01, MSM_SAW_BASE + 0x24); /* MSM_SPM_REG_SAW_SLP_CLK_EN */
+       writel(0x03, MSM_SAW_BASE + 0x28);
+       /* MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN */
+       writel(0x00, MSM_SAW_BASE + 0x2C);
+       /* MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN */
+       writel(0x01, MSM_SAW_BASE + 0x30); /* MSM_SPM_REG_SAW_SLP_CLMP_EN */
+       writel(0x00, MSM_SAW_BASE + 0x34); /* MSM_SPM_REG_SAW_SLP_RST_EN */
+       writel(0x00, MSM_SAW_BASE + 0x38); /* MSM_SPM_REG_SAW_SPM_MPM_CFG */
+}
+
+/* Configures msmc2 voltage. vlevel is in mV */
+void msmc2_config(unsigned vlevel)
+{
+       unsigned val;
+       val = readl(MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */
+       val &= ~0xFF;
+       val |= VDD_RAW(vlevel);
+       writel(val, MSM_SAW_BASE + 0x08); /* MSM_SPM_REG_SAW_VCTL */
+       /* Wait for PMIC state to return to idle and for VDD to stabilize */
+       while (((readl(MSM_SAW_BASE + 0x0C) >> 20) & 0x3) != 0)
+               ;
+       udelay(160);
+}
+
+void enable_pll(unsigned num)
+{
+       unsigned reg_val;
+       reg_val = readl(PLL_ENA_REG);
+       reg_val |= (1 << num);
+       writel(reg_val, PLL_ENA_REG);
+       /* Wait until PLL is enabled */
+       while ((readl(PLL2_STATUS_BASE_REG) & (1 << 16)) == 0)
+               ;
+}
+
+void acpu_clock_init(void)
+{
+       unsigned clk, reg_clksel, reg_clkctl, src_sel;
+       /* Fixing msmc2 voltage */
+       spm_init();
+       clk = readl(PLL2_L_VAL_ADDR) & 0xFF;
+       if (clk == ACPU_806MHZ)
+               msmc2_config(1100);
+       else if (clk == ACPU_1024MHZ || clk == ACPU_1200MHZ)
+               msmc2_config(1200);
+       else if (clk == ACPU_1400MHZ)
+               msmc2_config(1250);
+       /* Enable pll 2 */
+       enable_pll(2);
+       reg_clksel = readl(SCSS_CLK_SEL);
+       /* CLK_SEL_SRC1NO */
+       src_sel = reg_clksel & 1;
+       /* Program clock source and divider. */
+       reg_clkctl = readl(SCSS_CLK_CTL);
+       reg_clkctl &= ~(0xFF << (8 * src_sel));
+       reg_clkctl |= ACPU_SRC_SEL << (4 + 8 * src_sel);
+       reg_clkctl |= ACPU_SRC_DIV << (0 + 8 * src_sel);
+       writel(reg_clkctl, SCSS_CLK_CTL);
+       /* Toggle clock source. */
+       reg_clksel ^= 1;
+       /* Program clock source selection. */
+       writel(reg_clksel, SCSS_CLK_SEL);
+}
+
+void hsusb_clock_init(void)
+{
+       int val = 0;
+       unsigned sh2_own_row2;
+       unsigned sh2_own_row2_hsusb_mask = (1 << 11);
+
+       sh2_own_row2 = readl(SH2_OWN_ROW2_BASE_REG);
+       if (sh2_own_row2 & sh2_own_row2_hsusb_mask) {
+               /* USB local clock control enabled */
+               /* Set value in MD register */
+               val = 0x5DF;
+               writel(val, SH2_USBH_MD_REG);
+               /* Set value in NS register */
+               val = 1 << 8;
+               val = val | readl(SH2_USBH_NS_REG);
+               writel(val, SH2_USBH_NS_REG);
+               val = 1 << 11;
+               val = val | readl(SH2_USBH_NS_REG);
+               writel(val, SH2_USBH_NS_REG);
+               val = 1 << 9;
+               val = val | readl(SH2_USBH_NS_REG);
+               writel(val, SH2_USBH_NS_REG);
+               val = 1 << 13;
+               val = val | readl(SH2_USBH_NS_REG);
+               writel(val, SH2_USBH_NS_REG);
+               /* Enable USBH_P_CLK */
+               val = 1 << 25;
+               val = val | readl(SH2_GLBL_CLK_ENA_SC);
+               writel(val, SH2_GLBL_CLK_ENA_SC);
+       } else
+               /* USB local clock control not enabled; use proc comm */
+               usb_clock_init();
+
+}
+
+void adm_enable_clock(void)
+{
+       unsigned int val = 0;
+
+       /* Enable ADM_CLK */
+       val = 1 << 5;
+       val = val | readl(SH2_GLBL_CLK_ENA_SC);
+       writel(val, SH2_GLBL_CLK_ENA_SC);
+}
+
+void mdp_lcdc_clock_init(void)
+{
+       unsigned int val = 0;
+       unsigned sh2_own_apps2;
+       unsigned sh2_own_apps2_lcdc_mask = (1 << 3);
+
+       sh2_own_apps2 = readl(SH2_OWN_APPS2_BASE_REG);
+       if (sh2_own_apps2 & sh2_own_apps2_lcdc_mask) {
+               /* MDP local clock control enabled */
+               /* Select clock source and divider */
+               val = 0x29;
+               val = val | readl(SH2_MDP_NS_REG);
+               writel(val, SH2_MDP_NS_REG);
+
+               /* Enable MDP source clock(root) */
+               val = 1 << 11;
+               val = val | readl(SH2_MDP_NS_REG);
+               writel(val, SH2_MDP_NS_REG);
+
+               /* Enable graphics clock(branch) */
+               val = 1 << 9;
+               val = val | readl(SH2_MDP_NS_REG);
+               writel(val, SH2_MDP_NS_REG);
+
+               /* Enable MDP_P_CLK */
+               val = 1 << 6;
+               val = val | readl(SH2_GLBL_CLK_ENA_2_SC);
+               writel(val, SH2_GLBL_CLK_ENA_2_SC);
+
+               /* Enable AXI_MDP_CLK */
+               val = 1 << 29;
+               val = val | readl(SH2_GLBL_CLK_ENA_2_SC);
+               writel(val, SH2_GLBL_CLK_ENA_2_SC);
+
+               /* LCDC local clock control enabled */
+               /* Set value in MD register */
+               val = 0x1FFF9;
+               writel(val, SH2_MDP_LCDC_MD_REG);
+
+               /* Set MDP_LCDC_N_VAL in NS register */
+               val = 0xFFFA << 16;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+
+               /* Set clock source */
+               val = 1;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+
+               /* Set divider */
+               val = 3 << 3;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+
+               /* Set MN counter mode */
+               val = 2 << 5;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+
+               /* Enable MN counter */
+               val = 1 << 8;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+
+               /* Enable mdp_lcdc_src(root) clock */
+               val = 1 << 11;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+
+               /* Enable mdp_lcdc_pclk(branch) clock */
+               val = 1 << 9;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+
+               /* Enable mdp_lcdc_pad_pclk(branch) clock */
+               val = 1 << 12;
+               val = val | readl(SH2_MDP_LCDC_NS_REG);
+               writel(val, SH2_MDP_LCDC_NS_REG);
+       } else {
+               /* MDP local clock control not enabled; use proc comm */
+               mdp_clock_init(122880000);
+               /* LCDC local clock control not enabled; use proc comm */
+               lcdc_clock_init(27648000);
+       }
+}
+
+void mddi_pmdh_clock_init(void)
+{
+       unsigned int val = 0;
+       unsigned sh2_own_row1;
+       unsigned sh2_own_row1_pmdh_mask = (1 << 19);
+
+       sh2_own_row1 = readl(SH2_OWN_ROW1_BASE_REG);
+       if (sh2_own_row1 & sh2_own_row1_pmdh_mask) {
+               /* Select clock source and divider */
+               val = 1;
+               val |= (1 << 3);
+               val = val | readl(SH2_PMDH_NS_REG);
+               writel(val, SH2_PMDH_NS_REG);
+
+               /* Enable PMDH_SRC (root) signal */
+               val = 1 << 11;
+               val = val | readl(SH2_PMDH_NS_REG);
+               writel(val, SH2_PMDH_NS_REG);
+
+               /* Enable PMDH_P_CLK */
+               val = 1 << 4;
+               val = val | readl(SH2_GLBL_CLK_ENA_2_SC);
+               writel(val, SH2_GLBL_CLK_ENA_2_SC);
+       } else
+               /* MDDI local clock control not enabled; use proc comm */
+               mddi_clock_init(0, 480000000);
+}
+
+void ce_clock_init(void)
+{
+       unsigned int val = 0;
+
+       /* Enable CE_CLK */
+       val = 1 << 6;
+       val = val | readl(SH2_GLBL_CLK_ENA_SC);
+       writel(val, SH2_GLBL_CLK_ENA_SC);
+}
+
+#ifdef CONFIG_QC_MMC
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+       uint32_t reg = 0;
+
+       if (mmc_clock_set_rate(sdc_clk[interface], freq) < 0)
+               printf("Failure setting clock rate for MCLK - "
+                                                 "clk_rate: %d\n!", freq);
+
+       /* enable clock */
+       if (mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0)
+               printf("Failure enabling MMC Clock!\n");
+
+       reg |= MMC_BOOT_MCI_CLK_ENABLE;
+       reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
+       reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
+       writel(reg, MMC_BOOT_MCI_CLK);
+}
+
+/* Intialize MMC clock */
+void clock_init_mmc(uint32_t interface)
+{
+       if (mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0)
+               printf("Failure enabling PCLK!\n");
+}
+#endif
diff --git a/arch/arm/cpu/armv7/msm7630/board.c b/arch/arm/cpu/armv7/msm7630/board.c
new file mode 100644
index 0000000..c7b8204
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/board.c
@@ -0,0 +1,57 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/sys_proto.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void set_vector_base(unsigned long addr)
+{
+       __asm__ volatile ("mcr   p15, 0, %0, c12, c0, 0" : : "r" (addr));
+}
+
+int dram_init(void)
+{
+       /* We do not initialise DRAM here. We just query the size */
+       gd->ram_size = PHYS_SDRAM_1_SIZE;
+       return 0;
+}
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init()
+{
+       __cpu_early_init();
+       return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/msm7630/config.mk b/arch/arm/cpu/armv7/msm7630/config.mk
new file mode 100644
index 0000000..935a147
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/config.mk
@@ -0,0 +1 @@ 
+PLATFORM_CPPFLAGS += -march=armv7-a
diff --git a/arch/arm/cpu/armv7/msm7630/gpio.c b/arch/arm/cpu/armv7/msm7630/gpio.c
new file mode 100644
index 0000000..daa6d66
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/gpio.c
@@ -0,0 +1,229 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/proc_comm.h>
+#include <asm/arch/gpio_hw.h>
+
+struct gpioregs {
+       unsigned out;
+       unsigned in;
+       unsigned int_status;
+       unsigned int_clear;
+       unsigned int_en;
+       unsigned int_edge;
+       unsigned int_pos;
+       unsigned oe;
+};
+
+static struct gpioregs GPIO_REGS[] = {
+       {
+               .out =          GPIO_OUT_0,
+               .in =           GPIO_IN_0,
+               .int_status =   GPIO_INT_STATUS_0,
+               .int_clear =    GPIO_INT_CLEAR_0,
+               .int_en =       GPIO_INT_EN_0,
+               .int_edge =     GPIO_INT_EDGE_0,
+               .int_pos =      GPIO_INT_POS_0,
+               .oe =           GPIO_OE_0,
+       },
+       {
+               .out =          GPIO_OUT_1,
+               .in =           GPIO_IN_1,
+               .int_status =   GPIO_INT_STATUS_1,
+               .int_clear =    GPIO_INT_CLEAR_1,
+               .int_en =       GPIO_INT_EN_1,
+               .int_edge =     GPIO_INT_EDGE_1,
+               .int_pos =      GPIO_INT_POS_1,
+               .oe =           GPIO_OE_1,
+       },
+       {
+               .out =          GPIO_OUT_2,
+               .in =           GPIO_IN_2,
+               .int_status =   GPIO_INT_STATUS_2,
+               .int_clear =    GPIO_INT_CLEAR_2,
+               .int_en =       GPIO_INT_EN_2,
+               .int_edge =     GPIO_INT_EDGE_2,
+               .int_pos =      GPIO_INT_POS_2,
+               .oe =           GPIO_OE_2,
+       },
+       {
+               .out =          GPIO_OUT_3,
+               .in =           GPIO_IN_3,
+               .int_status =   GPIO_INT_STATUS_3,
+               .int_clear =    GPIO_INT_CLEAR_3,
+               .int_en =       GPIO_INT_EN_3,
+               .int_edge =     GPIO_INT_EDGE_3,
+               .int_pos =      GPIO_INT_POS_3,
+               .oe =           GPIO_OE_3,
+       },
+       {
+               .out =          GPIO_OUT_4,
+               .in =           GPIO_IN_4,
+               .int_status =   GPIO_INT_STATUS_4,
+               .int_clear =    GPIO_INT_CLEAR_4,
+               .int_en =       GPIO_INT_EN_4,
+               .int_edge =     GPIO_INT_EDGE_4,
+               .int_pos =      GPIO_INT_POS_4,
+               .oe =           GPIO_OE_4,
+       },
+       {
+               .out =          GPIO_OUT_5,
+               .in =           GPIO_IN_5,
+               .int_status =   GPIO_INT_STATUS_5,
+               .int_clear =    GPIO_INT_CLEAR_5,
+               .int_en =       GPIO_INT_EN_5,
+               .int_edge =     GPIO_INT_EDGE_5,
+               .int_pos =      GPIO_INT_POS_5,
+               .oe =           GPIO_OE_5,
+       },
+       {
+               .out =          GPIO_OUT_6,
+               .in =           GPIO_IN_6,
+               .int_status =   GPIO_INT_STATUS_6,
+               .int_clear =    GPIO_INT_CLEAR_6,
+               .int_en =       GPIO_INT_EN_6,
+               .int_edge =     GPIO_INT_EDGE_6,
+               .int_pos =      GPIO_INT_POS_6,
+               .oe =           GPIO_OE_6,
+       },
+       {
+               .out =          GPIO_OUT_7,
+               .in =           GPIO_IN_7,
+               .int_status =   GPIO_INT_STATUS_7,
+               .int_clear =    GPIO_INT_CLEAR_7,
+               .int_en =       GPIO_INT_EN_7,
+               .int_edge =     GPIO_INT_EDGE_7,
+               .int_pos =      GPIO_INT_POS_7,
+               .oe =           GPIO_OE_7,
+       },
+};
+
+static struct gpioregs *find_gpio(unsigned n, unsigned *bit)
+{
+       if (n > 150) {
+               *bit = 1 << (n - 151);
+               return GPIO_REGS + 7;
+       }
+       if (n > 133) {
+               *bit = 1 << (n - 134);
+               return GPIO_REGS + 6;
+       }
+       if (n > 106) {
+               *bit = 1 << (n - 107);
+               return GPIO_REGS + 5;
+       }
+       if (n > 94) {
+               *bit = 1 << (n - 95);
+               return GPIO_REGS + 4;
+       }
+       if (n > 67) {
+               *bit = 1 << (n - 68);
+               return GPIO_REGS + 3;
+       }
+       if (n > 43) {
+               *bit = 1 << (n - 44);
+               return GPIO_REGS + 2;
+       }
+       if (n > 15) {
+               *bit = 1 << (n - 16);
+               return GPIO_REGS + 1;
+       }
+       *bit = 1 << n;
+       return GPIO_REGS + 0;
+}
+
+int gpio_config(unsigned n, unsigned flags)
+{
+       struct gpioregs *r;
+       unsigned b;
+       unsigned v;
+
+       r = find_gpio(n, &b);
+       if (!r)
+               return -1;
+
+       v = readl(r->oe);
+       if (flags & GPIO_OUTPUT)
+               writel(v | b, r->oe);
+       else
+               writel(v & (~b), r->oe);
+       return 0;
+}
+
+void gpio_set(unsigned n, unsigned on)
+{
+       struct gpioregs *r;
+       unsigned b;
+       unsigned v;
+
+       r = find_gpio(n, &b);
+       if (r == 0)
+               return;
+
+       v = readl(r->out);
+       if (on)
+               writel(v | b, r->out);
+       else
+               writel(v & (~b), r->out);
+}
+
+int gpio_get(unsigned n)
+{
+       struct gpioregs *r;
+       unsigned b;
+
+       r = find_gpio(n, &b);
+       if (r  == 0)
+               return 0;
+       return (readl(r->in) & b) ? 1 : 0;
+}
+
+void platform_config_interleaved_mode_gpios(void)
+{
+       /* configure EB2_CS1 through GPIO86 */
+       writel(GPIO_ALT_FUNC_PAGE_REG, 0x56);
+       writel(GPIO_ALT_FUNC_CFG_REG, 0x04);
+       /* configure the EBI2_BUSY1_N through GPIO115 */
+       writel(GPIO_ALT_FUNC_PAGE_REG, 0x73);
+       writel(GPIO_ALT_FUNC_CFG_REG, 0x08);
+}
+
+/* Enables all gpios passed in table*/
+int platform_gpios_enable(const struct msm_gpio *table, int size)
+{
+       int rc;
+       int i;
+       const struct msm_gpio *g;
+       for (i = 0; i < size; i++) {
+               g = table + i;
+               /* Enable gpio */
+               rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
+               if (rc)
+                       goto err;
+       }
+       return 0;
+err:
+       return rc;
+}
+
diff --git a/arch/arm/cpu/armv7/msm7630/lowlevel_init.S b/arch/arm/cpu/armv7/msm7630/lowlevel_init.S
new file mode 100644
index 0000000..ef63770
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/lowlevel_init.S
@@ -0,0 +1,623 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+
+.text
+.code 32
+
+#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
+#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
+
+/*
+ ; LVT Ring Osc counter
+ ; used to determine sense amp settings
+ ; Clobbers registers r0, r4, r5, r6, r7, r9, r10, r11
+*/
+.equ CLK_CTL_BASE,     0xA8600000
+.equ A_GLBL_CLK_ENA,   0x0000
+.equ A_PRPH_WEB_NS_REG,0x0080
+.equ A_MSM_CLK_RINGOSC,0x00D0
+.equ A_TCXO_CNT,       0x00D4
+.equ A_TCXO_CNT_DONE,  0x00D8
+.equ A_RINGOSC_CNT,    0x00DC
+.equ A_MISC_CLK_CTL,   0x0108
+.equ CLK_TEST,         0xA8600114
+.equ SPSS_CSR_BASE,    0xAC100000
+.equ A_SCRINGOSC,      0x0510
+
+//;; Number of TCXO cycles to count ring oscillations
+.equ TCXO_CNT_VAL,     0x100
+
+//; Halcyon addresses
+.equ TCSR_CONF_FUSE_1, 0xAB600060 //; TCSR_CONF_FUSE_1 register
+.equ TCSR_CONF_FUSE_4, 0xAB60006C //; TCSR_CONF_FUSE_4 register
+
+//; SCORPION_L1_ACC (1:0) Fuses bit location
+.equ L1_ACC_BIT_0,     12       //;12th bit of TCSR_CONF_FUSE_4
+.equ L1_ACC_BIT_1,     13       //;13th bit of TCSR_CONF_FUSE_4
+//; SCORPION_L2_ACC (2:0) Fuses bit location
+.equ L2_ACC_BIT_0,     25       //;25th bit of TCSR_CONF_FUSE_1
+.equ L2_ACC_BIT_1,     10       //;10th bit of TCSR_CONF_FUSE_4
+.equ L2_ACC_BIT_2,     11       //;11th bit of TCSR_CONF_FUSE_4
+
+//; CP15: PVR2F0 values according to  SCORPION_L1_ACC (1:0)
+.equ PVR2F0_00,        0x00000000
+.equ PVR2F0_01,        0x04000000
+.equ PVR2F0_10,        0x08000000
+.equ PVR2F0_11,        0x0C000000
+
+//; CP15: PVR2F1 values according to  SCORPION_L1_ACC (1:0)
+.equ PVR2F1_00,        0x00000008
+.equ PVR2F1_01,        0x00000008
+.equ PVR2F1_10,        0x00000208
+.equ PVR2F1_11,        0x00000208
+
+//; CP15: PVR0F2 values according to  SCORPION_L1_ACC (1:0)
+.equ PVR0F2_00,        0x00000000
+.equ PVR0F2_01,        0x00000000
+.equ PVR0F2_10,        0x00000200
+.equ PVR0F2_11,        0x00000200
+
+//; CP15: PVR0F0 values according to  SCORPION_L1_ACC (1:0)
+.equ PVR0F0_00,        0x7F000000
+.equ PVR0F0_01,        0x7F000400
+.equ PVR0F0_10,        0x7F000000
+.equ PVR0F0_11,        0x7F000400
+
+//; CP15: L2VR3F1 values according to  SCORPION_L2_ACC (2:0)
+.equ L2VR3F1_000,      0x00FFFF60
+.equ L2VR3F1_001,      0x00FFFF40
+.equ L2VR3F1_010,      0x00FFFC60
+.equ L2VR3F1_011,      0x00FFFC40
+.equ L2VR3F1_100,      0x00FCFF60
+.equ L2VR3F1_101,      0x00FCFF40
+.equ L2VR3F1_110,      0x00FCFC60
+.equ L2VR3F1_111,      0x00FCFC40
+
+
+
+
+_TEXT_BASE:
+       .word   CONFIG_SYS_TEXT_BASE    @ sdram load addr from config file
+
+.global invalidate_dcache
+invalidate_dcache:
+       mov pc, lr
+
+       .align  5
+.globl lowlevel_init
+lowlevel_init:
+       mov     pc, lr                          @ back to arch calling code
+
+.global reset_cpu
+reset_cpu:
+_loop_forever:
+        b       _loop_forever
+
+.globl SET_SA
+SET_SA:
+
+        //;--------------------------------------------------------------------
+        //; Fuse bits used to determine sense amp settings
+        //;--------------------------------------------------------------------
+
+        //; Reading L1_ACC
+        ldr    r4, = 0x0
+
+        //; Read L1_ACC_BIT_0
+        ldr    r1, =TCSR_CONF_FUSE_4
+        ldr    r2, =L1_ACC_BIT_0
+        ldr    r3, [r1]
+        mov    r3, r3, LSR r2
+        and    r3, r3, #1
+        orr    r4, r3, r4
+
+        //; Read L1_ACC_BIT_1
+        ldr    r1, =TCSR_CONF_FUSE_4
+        ldr    r2, =L1_ACC_BIT_1
+        ldr    r3, [r1]
+        mov    r3, r3, LSR r2
+        and    r3, r3, #1
+        mov    r3, r3, LSL #1
+        orr    r4, r3, r4
+
+l1_ck_0:
+        //; if L1_[1:0] == 00
+        ldr    r5, = 0x0
+        cmp    r4, r5
+        bne    l1_ck_1
+        ldr    r0, =PVR0F0_00
+        ldr    r1, =PVR0F2_00
+        ldr    r2, =PVR2F0_00
+        ldr    r3, =PVR2F1_00
+        b      WRITE_L1_SA_SETTINGS
+
+l1_ck_1:
+        //; if L1_[1:0] == 01
+        ldr    r1, = 0x01
+        cmp    r4, r1
+        bne    l1_ck_2
+        ldr    r0, =PVR0F0_01
+        ldr    r1, =PVR0F2_01
+        ldr    r2, =PVR2F0_01
+        ldr    r3, =PVR2F1_01
+        b      WRITE_L1_SA_SETTINGS
+
+l1_ck_2:
+        //; if L1_[2:0] == 10
+        ldr    r1, = 0x02
+        cmp    r4, r1
+        bne    l1_ck_3
+        ldr    r0, =PVR0F0_10
+        ldr    r1, =PVR0F2_10
+        ldr    r2, =PVR2F0_10
+        ldr    r3, =PVR2F1_10
+        b      WRITE_L1_SA_SETTINGS
+
+l1_ck_3:
+        //; if L1_[2:0] == 11
+        ldr    r1, = 0x03
+        cmp    r4, r1
+        ldr    r0, =PVR0F0_11
+        ldr    r1, =PVR0F2_11
+        ldr    r2, =PVR2F0_11
+        ldr    r3, =PVR2F1_11
+        b      WRITE_L1_SA_SETTINGS
+
+
+WRITE_L1_SA_SETTINGS:
+
+        //;WCP15_PVR0F0   r0
+        mcr    p15, 0x0, r0, c15, c15, 0x0   //; write R0 to PVR0F0
+
+        //;WCP15_PVR0F2   r1
+        mcr    p15, 0x0, r1, c15, c15, 0x2   //; write R1 to PVR0F2
+
+        //;WCP15_PVR2F0   r2
+        mcr    p15, 0x2, r2, c15, c15, 0x0   //; write R2 to PVR2F0
+
+        // Disable predecode repair cache on certain Scorpion revisions
+        // (Raptor V2 and earlier, or Halcyon V1)
+        mrc    p15, 0, r1, c0, c0, 0      //; MIDR
+        BIC    r2, r1, #0xf0              //; check for Halcyon V1
+        ldr    r4, =0x511f0000
+        cmp    r2, r4
+        bne    PVR2F1
+
+DPRC:
+        mrc    p15, 0, r1, c15, c15, 2    //; PVR0F2
+        orr    r1, r1, #0x10              //; enable bit 4
+        mcr    p15, 0, r1, c15, c15, 2    //; disable predecode repair cache
+
+PVR2F1:
+        //;WCP15_PVR2F1   r3
+        mcr    p15, 0x2, r3, c15, c15, 0x1   //; write R3 to PVR2F1
+
+        //; Reading L2_ACC
+        ldr    r4, = 0x0
+
+        //; Read L2_ACC_BIT_0
+        ldr    r1, =TCSR_CONF_FUSE_1
+        ldr    r2, =L2_ACC_BIT_0
+        ldr    r3, [r1]
+        mov    r3, r3, LSR r2
+        and    r3, r3, #1
+        orr    r4, r3, r4
+
+        //; Read L2_ACC_BIT_1
+        ldr    r1, =TCSR_CONF_FUSE_4
+        ldr    r2, =L2_ACC_BIT_1
+        ldr    r3, [r1]
+        mov    r3, r3, LSR r2
+        and    r3, r3, #1
+        mov    r3, r3, LSL #1
+        orr    r4, r3, r4
+
+        //; Read L2_ACC_BIT_2
+        ldr    r1, =TCSR_CONF_FUSE_4
+        ldr    r2, =L2_ACC_BIT_2
+        ldr    r3, [r1]
+        mov    r3, r3, LSR r2
+        and    r3, r3, #1
+        mov    r3, r3, LSL #2
+        orr    r4, r3, r4
+
+l2_ck_0:
+        //; if L2_[2:0] == 000
+        ldr    r5, = 0x0
+        cmp    r4, r5
+        bne    l2_ck_1
+        ldr    r0, =L2VR3F1_000
+        b      WRITE_L2_SA_SETTINGS
+
+l2_ck_1:
+        //; if L2_[2:0] == 001
+        ldr     r5, = 0x1
+        cmp     r4, r5
+        bne     l2_ck_2
+        ldr     r0, =L2VR3F1_001
+        b       WRITE_L2_SA_SETTINGS
+
+l2_ck_2:
+        //; if L2_[2:0] == 010
+        ldr    r5, = 0x2
+        cmp    r4, r5
+        bne    l2_ck_3
+        ldr    r0, =L2VR3F1_010
+        b      WRITE_L2_SA_SETTINGS
+
+l2_ck_3:
+        //; if L2_[2:0] == 011
+        ldr    r5, = 0x3
+        cmp    r4, r5
+        bne    l2_ck_4
+        ldr    r0, =L2VR3F1_011
+        b      WRITE_L2_SA_SETTINGS
+
+l2_ck_4:
+        //; if L2_[2:0] == 100
+        ldr    r5, = 0x4
+        cmp    r4, r5
+        bne    l2_ck_5
+        ldr    r0, =L2VR3F1_100
+        b      WRITE_L2_SA_SETTINGS
+
+l2_ck_5:
+        //; if L2_[2:0] == 101
+        ldr    r5, = 0x5
+        cmp    r4, r5
+        bne    l2_ck_6
+        ldr    r0, =L2VR3F1_101
+        b      WRITE_L2_SA_SETTINGS
+
+l2_ck_6:
+        //; if L2_[2:0] == 110
+        ldr    r5, = 0x6
+        cmp    r4, r5
+        bne    l2_ck_7
+        ldr    r0, =L2VR3F1_110
+        b      WRITE_L2_SA_SETTINGS
+
+l2_ck_7:
+        //; if L2_[2:0] == 111
+        ldr    r5, = 0x7
+        cmp    r4, r5
+        ldr    r0, =L2VR3F1_111
+        b      WRITE_L2_SA_SETTINGS
+
+WRITE_L2_SA_SETTINGS:
+        //;WCP15_L2VR3F1  r0
+        mcr    p15, 0x3, r0, c15, c15, 0x1     //;write r0 to L2VR3F1
+       DSB
+       ISB
+
+        ldr    r0, =0                   //;make sure the registers we touched
+        ldr    r1, =0                   //;are cleared when we return
+        ldr    r2, =0
+        ldr    r3, =0
+        ldr    r4, =0
+        ldr    r5, =0
+
+       mrs     r0, cpsr
+       orr     r0, r0, #(1<<7)
+       msr     cpsr_c, r0
+
+       //; routine complete
+       pop     {r5-r12,pc}
+
+.ltorg
+
+.globl __cpu_early_init
+__cpu_early_init:
+
+        //; Zero out r0 for use throughout this code. All other GPRs
+        //; (r1-r3) are set throughout this code to help establish
+        //; a consistent startup state for any code that follows.
+        //; Users should add code at the end of this routine to establish
+        //; their own stack address (r13), add translation page tables, enable
+        //; the caches, etc.
+       push    {r5-r12,r14}
+        mov    r0,  #0x0
+
+
+        //; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
+        //;   API to dynamically configure cache for slow/nominal/fast parts
+
+        //; DCIALL to invalidate L2 cache bank (needs to be run 4 times,
+       //; once per bank)
+        //; This must be done early in code (prior to enabling the caches)
+        mov    r1, #0x2
+        mcr    p15, 0, r1, c9, c0, 6   //; DCIALL bank D ([15:14] == 2'b00)
+        orr    r1, r1, #0x00004000
+        mcr    p15, 0, r1, c9, c0, 6   //; DCIALL bank C ([15:14] == 2'b01)
+        add    r1, r1, #0x00004000
+        mcr    p15, 0, r1, c9, c0, 6   //; DCIALL bank B ([15:14] == 2'b10)
+        add    r1, r1, #0x00004000
+        mcr    p15, 0, r1, c9, c0, 6   //; DCIALL bank A ([15:14] == 2'b11)
+
+        //; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
+        //; and have all address bits (AM) participate.
+        //; Different settings can be used to improve performance
+        // movW   r1, #0x01FF
+.word 0xe30011ff  // hardcoded movW instruction due to lack of compiler support
+        // movT   r1, #0x01FF
+.word 0xe34011ff  // hardcoded movT instruction due to lack of compiler support
+        mcr    p15, 7, r1, c15, c0, 2   //; WCP15_BPCR
+
+
+        //; Initialize all I$ Victim Registers to 0 for startup
+        mcr    p15, 0, r0, c9, c1, 0    //; WCP15_ICVIC0    r0
+        mcr    p15, 0, r0, c9, c1, 1    //; WCP15_ICVIC1    r0
+        mcr    p15, 0, r0, c9, c1, 2    //; WCP15_ICVIC2    r0
+        mcr    p15, 0, r0, c9, c1, 3    //; WCP15_ICVIC3    r0
+        mcr    p15, 0, r0, c9, c1, 4    //; WCP15_ICVIC4    r0
+        mcr    p15, 0, r0, c9, c1, 5    //; WCP15_ICVIC5    r0
+        mcr    p15, 0, r0, c9, c1, 6    //; WCP15_ICVIC5    r0
+        mcr    p15, 0, r0, c9, c1, 7    //; WCP15_ICVIC7    r0
+
+        //; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
+        mcr    p15, 1, r0, c9, c1, 0    //; WCP15_ICFLOOR0  r0
+        mcr    p15, 1, r0, c9, c1, 1    //; WCP15_ICFLOOR1  r0
+        mcr    p15, 1, r0, c9, c1, 2    //; WCP15_ICFLOOR2  r0
+        mcr    p15, 1, r0, c9, c1, 3    //; WCP15_ICFLOOR3  r0
+        mcr    p15, 1, r0, c9, c1, 4    //; WCP15_ICFLOOR4  r0
+        mcr    p15, 1, r0, c9, c1, 5    //; WCP15_ICFLOOR5  r0
+        mcr    p15, 1, r0, c9, c1, 6    //; WCP15_ICFLOOR6  r0
+        mcr    p15, 1, r0, c9, c1, 7    //; WCP15_ICFLOOR7  r0
+
+        //; Initialize all D$ Victim Registers to 0
+        mcr    p15, 2, r0, c9, c1, 0    //; WP15_DCVIC0    r0
+        mcr    p15, 2, r0, c9, c1, 1    //; WP15_DCVIC1    r0
+        mcr    p15, 2, r0, c9, c1, 2    //; WP15_DCVIC2    r0
+        mcr    p15, 2, r0, c9, c1, 3    //; WP15_DCVIC3    r0
+        mcr    p15, 2, r0, c9, c1, 4    //; WP15_DCVIC4    r0
+        mcr    p15, 2, r0, c9, c1, 5    //; WP15_DCVIC5    r0
+        mcr    p15, 2, r0, c9, c1, 6    //; WP15_DCVIC6    r0
+        mcr    p15, 2, r0, c9, c1, 7    //; WP15_DCVIC7    r0
+
+        //; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
+        mcr    p15, 3, r0, c9, c1, 0    //; WCP15_DCFLOOR0  r0
+        mcr    p15, 3, r0, c9, c1, 1    //; WCP15_DCFLOOR1  r0
+        mcr    p15, 3, r0, c9, c1, 2    //; WCP15_DCFLOOR2  r0
+        mcr    p15, 3, r0, c9, c1, 3    //; WCP15_DCFLOOR3  r0
+        mcr    p15, 3, r0, c9, c1, 4    //; WCP15_DCFLOOR4  r0
+        mcr    p15, 3, r0, c9, c1, 5    //; WCP15_DCFLOOR5  r0
+        mcr    p15, 3, r0, c9, c1, 6    //; WCP15_DCFLOOR6  r0
+        mcr    p15, 3, r0, c9, c1, 7    //; WCP15_DCFLOOR7  r0
+
+        //; Initialize ASID to zero
+        mcr    p15, 0, r0, c13, c0, 1   //; WCP15_CONTEXTIDR r0
+
+        //; ICIALL to invalidate entire I-Cache
+        mcr    p15, 0, r0, c7, c5, 0    //; ICIALLU
+
+        //; DCIALL to invalidate entire D-Cache
+        mcr    p15, 0, r0, c9, c0, 6    //; DCIALL  r0
+
+       //; Initialize ADFSR to zero
+        mcr    p15, 0, r0, c5, c1, 0    //; ADFSR   r0
+
+       //; Initialize EFSR to zero
+        mcr    p15, 7, r0, c15, c0, 1   //; EFSR    r0
+
+        //; The VBAR (Vector Base Address Register) should be initialized
+        //; early in your code. We are setting it to zero
+        mcr    p15, 0, r0, c12, c0, 0   //; WCP15_VBAR  r0
+
+        //; Ensure the mcr's above have completed their operation
+       //; before continuing
+        DSB
+        ISB
+
+        //; Setup CCPR - Cache Coherency Policy Register
+        //; setup CCPR[L1ISHP, L2ISHP] both to 0b00 (no forcing)
+        //; setup CCPR[L1OSHP, L2OSHP] both to 0b10 (force non-cacheable)
+        movw   r2, #0x88
+        mcr    p15, 0, r2, c10, c4, 2
+
+        //;-------------------------------------------------------------------
+        //; There are a number of registers that must be set prior to enabling
+        //; the MMU. The DCAR is one of these registers. We are setting
+        //; it to zero (no access) to easily detect improper setup in subsequent
+        //; code sequences
+        //;-------------------------------------------------------------------
+        //; Setup DACR (Domain Access Control Register) to zero
+        mcr    p15, 0, r0, c3, c0, 0    //; WCP15_DACR  r0
+
+        //; Setup DCLKCR to allow normal D-Cache line fills
+        mcr    p15, 1, r0, c9, c0, 7    //; WCP15_DCLKCR r0
+
+        //; Setup the TLBLKCR
+        //; Victim = 6'b000000; Floor = 6'b000000;
+        //; IASIDCFG =
+       //;2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
+        mov    r1, #0x02
+        mcr    p15, 0, r1, c10, c1, 3     //; WCP15_TLBLKCR  r1
+
+        //;Make sure TLBLKCR is complete before continuing
+        ISB
+
+        //; Invalidate the UTLB
+        mcr    p15, 0, r0, c8, c7, 0      //; UTLBIALL
+
+        //; Make sure UTLB request has been presented to macro before continuing
+        ISB
+
+SYSI2:
+        //; setup L2CR1 to some default Instruction and data prefetching values
+        //; Users may want specific settings for various performance
+       //; enhancements
+        //; In Halcyon we do not have broadcasting barriers. So we need to turn
+        //  ; on bit 8 of L2CR1; which DBB:( Disable barrier broadcast )
+        ldr    r2, =0x133
+        mcr    p15, 3, r2, c15, c0, 3     //; WCP15_L2CR1  r0
+
+
+        //; Enable Z bit to enable branch prediction (default is off)
+        mrc    p15, 0, r2, c1, c0, 0      //; RCP15_SCTLR  r2
+        orr    r2, r2, #0x00000800
+        mcr    p15, 0, r2, c1, c0, 0      //; WCP15_SCTLR  r2
+
+        //; Make sure Link stack is initialized with branch and links to
+       //; sequential addresses
+        //; This aids in creating a predictable startup environment
+        bl     SEQ1
+SEQ1:   bl     SEQ2
+SEQ2:   bl     SEQ3
+SEQ3:   bl     SEQ4
+SEQ4:   bl     SEQ5
+SEQ5:   bl     SEQ6
+SEQ6:   bl     SEQ7
+SEQ7:   bl     SEQ8
+SEQ8:
+
+        //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
+        //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the
+       //;debug registers
+        //; Writing anything but the "secret code" to the DBGOSLAR clears the
+       //;DBGOSLSR[LOCK] bit
+        mcr    p14, 0, r0, c1, c0, 4       //; WCP14_DBGOSLAR r0
+
+
+        //; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
+        //; Any read to DBGPRSR clear the STICKYPD bit
+        //; ISB guarantees the read completes before attempting to
+        //; execute a CP14 instruction.
+        mrc    p14, 0, r3, c1, c5, 4       //; RCP14_DBGPRSR r3
+        ISB
+
+
+
+        //;--------------------------------------------------------------------
+        //; The saved Program Status Registers (SPSRs) should be setup
+        //; prior to any automatic mode switches. The following
+        //; code sets these registers up to a known state. Users will need to
+        //; customize these settings to meet their needs.
+        //;--------------------------------------------------------------------
+        mov    r2,  #0x1f
+        mov    r1,  #0xd7                 //;ABT mode
+        msr    cpsr_c, r1                 //;ABT mode
+        msr    spsr_cxfs, r2              //;clear the spsr
+        mov    r1,  #0xdb                 //;UND mode
+        msr    cpsr_c, r1                 //;UND mode
+        msr    spsr_cxfs, r2              //;clear the spsr
+        mov    r1,  #0xd1                 //;FIQ mode
+        msr    cpsr_c, r1                 //;FIQ mode
+        msr    spsr_cxfs, r2              //;clear the spsr
+        mov    r1,  #0xd2                 //;IRQ mode
+        msr    cpsr_c, r1                 //;IRQ mode
+        msr    spsr_cxfs, r2              //;clear the spsr
+        mov    r1,  #0xd6                 //;Monitor mode
+        msr    cpsr_c, r1                 //;Monitor mode
+        msr    spsr_cxfs, r2              //;clear the spsr
+        mov    r1,  #0xd3                 //;SVC mode
+        msr    cpsr_c, r1                 //;SVC mode
+        msr    spsr_cxfs, r2              //;clear the spsr
+
+
+        //;--------------------------------------------------------------------
+        //; Enabling Error reporting is something users may want to do at
+        //; some other point in time. We have chosen some default settings
+        //; that should be reviewed. Most of these registers come up in an
+        //; unpredictable state after reset.
+        //;--------------------------------------------------------------------
+//;Start of error and control setting
+
+        //; setup L2CR0 with various L2/TCM control settings
+        //; enable out of order bus attributes and error reporting
+        //; this register comes up unpredictable after reset
+        // movw   r1, #0x0F0F
+.word 0xe3001f0f  // hardcoded movw instruction due to lack of compiler support
+        // movT   r1, #0xC005
+.word 0xe34c1005  // hardcoded movw instruction due to lack of compiler support
+        mcr    p15, 3, r1, c15, c0, 1    //; WCP15_L2CR0  r1
+
+        //; setup L2CPUCR
+        //; mov    r2, #0xFF
+        //; Enable I and D cache parity
+        //;L2CPUCR[7:5] = 3~Rh7 ~V enable parity error reporting for modified,
+        //;tag, and data parity errors
+        mov    r2, #0xe0
+        mcr    p15, 3, r2, c15, c0, 2    //; WCP15_L2CPUCR  r2
+
+        //; setup SPCR
+        //; enable all error reporting
+       //;(reset value is unpredicatble for most bits)
+        mov    r3, #0x0F
+        mcr    p15, 0, r3, c9, c7, 0     //; WCP15_SPCR  r3
+
+        //; setup DMACHCRs (reset value unpredictable)
+        //; control setting and enable all error reporting
+        mov    r1, #0x0F
+
+        //; DMACHCR0 = 0000000F
+        mov    r2, #0x00                  //; channel 0
+        mcr    p15, 0, r2, c11, c0, 0     //; WCP15_DMASELR  r2
+        mcr    p15, 0, r1, c11, c0, 2     //; WCP15_DMACHCR  r1
+
+        //; DMACHCR1 = 0000000F
+        mov    r2, #0x01                  //; channel 1
+        mcr    p15, 0, r2, c11, c0, 0     //; WCP15_DMASELR  r2
+        mcr    p15, 0, r1, c11, c0, 2     //; WCP15_DMACHCR  r1
+
+        //; DMACHCR2 = 0000000F
+        mov    r2, #0x02                  //; channel 2
+        mcr    p15, 0, r2, c11, c0, 0     //; WCP15_DMASELR  r2
+        mcr    p15, 0, r1, c11, c0, 2     //; WCP15_DMACHCR  r1
+
+        //; DMACHCR3 = 0000000F
+        mov    r2, #0x03                  //; channel 3
+        mcr    p15, 0, r2, c11, c0, 0     //; WCP15_DMASELR  r2
+        mcr    p15, 0, r1, c11, c0, 2     //; WCP15_DMACHCR  r1
+
+        //; Set ACTLR (reset unpredictable)
+        //; Set AVIVT control, error reporting, etc.
+        //; mov   r3, #0x07
+        //; Enable I and D cache parity
+        //;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
+        //;ACTLR[5:4] = 2'h3 - enable parity
+        //;ACTLR[19:18] =2'h3 - always generate and
+       //;check parity(when MMU disabled).
+        //;Value to be written #0xC0037
+        // movw   r3, #0x0037
+.word 0xe3003037  // hardcoded movw instruction due to lack of compiler support
+        // movT   r3, #0x000C
+.word 0xe340300c  // hardcoded movw instruction due to lack of compiler support
+        mcr    p15, 0, r3, c1, c0, 1      //; WCP15_ACTLR  r3
+
+//;End of error and control setting
+
+        //;---------------------------------------------------------------------
+        //; Unlock ETM and read StickyPD to halt the ETM clocks from running.
+        //; This is required for power saving whether the ETM is used or not.
+        //;---------------------------------------------------------------------
+
+        //;Clear ETMOSLSR[LOCK] bit
+        mov    r1, #0x00000000
+        mcr    p14, 1, r1, c1, c0, 4        //; WCP14_ETMOSLAR      r1
+
+        //;Clear ETMPDSR[STICKYPD] bit
+        mrc    p14, 1, r2, c1, c5, 4        //; RCP14_ETMPDSR       r2
+        b       SET_SA
+
+
+.ltorg
diff --git a/arch/arm/cpu/armv7/msm7630/timer.c b/arch/arm/cpu/armv7/msm7630/timer.c
new file mode 100644
index 0000000..007314e
--- /dev/null
+++ b/arch/arm/cpu/armv7/msm7630/timer.c
@@ -0,0 +1,142 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/iomap.h>
+#include <asm/io.h>
+#include <config.h>
+#include <common.h>
+#include <asm/types.h>
+#define TIMER_LOAD_VAL 0x21
+
+#define GPT_ENABLE_CLR_ON_MATCH_EN        2
+#define GPT_ENABLE_EN                     1
+#define DGT_ENABLE_CLR_ON_MATCH_EN        2
+#define DGT_ENABLE_EN                     1
+
+#define SPSS_TIMER_STATUS_DGT_EN    (1 << 0)
+
+
+#define READ_TIMER    readl(GPT_COUNT_VAL)
+
+static ulong timestamp;
+static ulong lastinc;
+#define DGT_HZ 6750000         /* Uses LPXO/4 (27.0 MHz / 4) */
+
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+       uint32_t val = 0;
+
+       /* Disable timer */
+       writel(0, DGT_ENABLE);
+
+       /* Check for the hardware revision */
+       val = readl(HW_REVISION_NUMBER);
+       val = (val >> 28) & 0x0F;
+       if (val >= 1)
+               writel(1, DGT_CLK_CTL);
+       return 0;
+}
+
+
+ulong get_timer(ulong base)
+{
+       return get_timer_masked() - base;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void __udelay(unsigned long usecs)
+{
+       unsigned int val;
+       usecs = (usecs * 33 + 1000 - 33) / 1000;
+
+       writel(0, GPT_CLEAR);
+       writel(0, GPT_ENABLE);
+       do {
+               val = 0;
+               val = readl(GPT_COUNT_VAL);
+       } while (val != 0);
+
+       writel(GPT_ENABLE_EN, GPT_ENABLE);
+       do {
+               val = 0;
+               val = readl(GPT_COUNT_VAL);
+       } while (val < usecs) ;
+
+       writel(0, GPT_ENABLE);
+       writel(0, GPT_CLEAR);
+
+}
+
+
+ulong get_timer_masked(void)
+{
+       ulong now = READ_TIMER; /* current tick value */
+
+       if (lastinc <= now) {   /* normal mode (non roll) */
+               /* normal mode */
+               timestamp += now - lastinc;
+               /* move stamp forward with absolute diff ticks */
+       } else {                /* we have overflow of the count down timer */
+               timestamp += now + (TIMER_LOAD_VAL - lastinc);
+       }
+       lastinc = now;
+
+       return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return 19200000;
+}
diff --git a/arch/arm/include/asm/arch-msm7630/adm.h b/arch/arm/include/asm/arch-msm7630/adm.h
new file mode 100644
index 0000000..0e8af85
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/adm.h
@@ -0,0 +1,28 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __ADM_H
+#define __ADM_H
+
+/* Channel #s and security domain */
+#define ADM_CHN         8
+#define ADM_SD          2
+
+#endif
diff --git a/arch/arm/include/asm/arch-msm7630/gpio.h b/arch/arm/include/asm/arch-msm7630/gpio.h
new file mode 100644
index 0000000..af6ddaa
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/gpio.h
@@ -0,0 +1,47 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __GPIO_H
+#define __GPIO_H
+
+#ifndef GPIO_INPUT
+#define GPIO_INPUT     0x0000
+#endif
+#ifndef GPIO_OUTPUT
+#define GPIO_OUTPUT    0x0001
+#endif
+
+#define GPIO_LEVEL     0x0000
+#define GPIO_EDGE      0x0010
+
+#define GPIO_RISING    0x0020
+#define GPIO_FALLING   0x0040
+
+#define GPIO_HIGH      0x0020
+#define GPIO_LOW       0x0040
+
+#define GPIO_PULLUP    0x0100
+#define GPIO_PULLDOWN  0x0200
+
+int gpio_config(unsigned nr, unsigned flags);
+void gpio_set(unsigned nr, unsigned on);
+int gpio_get(unsigned nr);
+
+#endif
diff --git a/arch/arm/include/asm/arch-msm7630/gpio_hw.h b/arch/arm/include/asm/arch-msm7630/gpio_hw.h
new file mode 100644
index 0000000..c8244d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/gpio_hw.h
@@ -0,0 +1,168 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __GPIO_HW_H
+#define __GPIO_HW_H
+
+#define MSM_GPIO1_BASE 0xAC001000
+#define MSM_GPIO2_BASE 0xAC101000
+
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
+
+/* output value */
+#define GPIO_OUT_0         GPIO1_REG(0x00)  /* gpio  15-0   */
+#define GPIO_OUT_1         GPIO2_REG(0x00)  /* gpio  43-16  */
+#define GPIO_OUT_2         GPIO1_REG(0x04)  /* gpio  67-44  */
+#define GPIO_OUT_3         GPIO1_REG(0x08)  /* gpio  94-68  */
+#define GPIO_OUT_4         GPIO1_REG(0x0C)  /* gpio 106-95  */
+#define GPIO_OUT_5         GPIO1_REG(0x50)  /* gpio 133-107 */
+#define GPIO_OUT_6         GPIO1_REG(0xC4)  /* gpio 150-134 */
+#define GPIO_OUT_7         GPIO1_REG(0x214)  /* gpio 181-151 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0          GPIO1_REG(0x10)
+#define GPIO_OE_1          GPIO2_REG(0x08)
+#define GPIO_OE_2          GPIO1_REG(0x14)
+#define GPIO_OE_3          GPIO1_REG(0x18)
+#define GPIO_OE_4          GPIO1_REG(0x1C)
+#define GPIO_OE_5          GPIO1_REG(0x54)
+#define GPIO_OE_6          GPIO1_REG(0xC8)
+#define GPIO_OE_7          GPIO1_REG(0x218)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0          GPIO1_REG(0x34)
+#define GPIO_IN_1          GPIO2_REG(0x20)
+#define GPIO_IN_2          GPIO1_REG(0x38)
+#define GPIO_IN_3          GPIO1_REG(0x3C)
+#define GPIO_IN_4          GPIO1_REG(0x40)
+#define GPIO_IN_5          GPIO1_REG(0x44)
+#define GPIO_IN_6          GPIO1_REG(0xCC)
+#define GPIO_IN_7          GPIO1_REG(0x21C)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define GPIO_INT_EDGE_0    GPIO1_REG(0x60)
+#define GPIO_INT_EDGE_1    GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2    GPIO1_REG(0x64)
+#define GPIO_INT_EDGE_3    GPIO1_REG(0x68)
+#define GPIO_INT_EDGE_4    GPIO1_REG(0x6C)
+#define GPIO_INT_EDGE_5    GPIO1_REG(0xC0)
+#define GPIO_INT_EDGE_6    GPIO1_REG(0xD0)
+#define GPIO_INT_EDGE_7    GPIO1_REG(0x240)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0     GPIO1_REG(0x70)
+#define GPIO_INT_POS_1     GPIO2_REG(0x58)
+#define GPIO_INT_POS_2     GPIO1_REG(0x74)
+#define GPIO_INT_POS_3     GPIO1_REG(0x78)
+#define GPIO_INT_POS_4     GPIO1_REG(0x7C)
+#define GPIO_INT_POS_5     GPIO1_REG(0xBC)
+#define GPIO_INT_POS_6     GPIO1_REG(0xD4)
+#define GPIO_INT_POS_7     GPIO1_REG(0x228)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0      GPIO1_REG(0x80)
+#define GPIO_INT_EN_1      GPIO2_REG(0x60)
+#define GPIO_INT_EN_2      GPIO1_REG(0x84)
+#define GPIO_INT_EN_3      GPIO1_REG(0x88)
+#define GPIO_INT_EN_4      GPIO1_REG(0x8C)
+#define GPIO_INT_EN_5      GPIO1_REG(0xB8)
+#define GPIO_INT_EN_6      GPIO1_REG(0xD8)
+#define GPIO_INT_EN_7      GPIO1_REG(0x22C)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0   GPIO1_REG(0x90)
+#define GPIO_INT_CLEAR_1   GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2   GPIO1_REG(0x94)
+#define GPIO_INT_CLEAR_3   GPIO1_REG(0x98)
+#define GPIO_INT_CLEAR_4   GPIO1_REG(0x9C)
+#define GPIO_INT_CLEAR_5   GPIO1_REG(0xB4)
+#define GPIO_INT_CLEAR_6   GPIO1_REG(0xDC)
+#define GPIO_INT_CLEAR_7   GPIO1_REG(0x230)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0  GPIO1_REG(0xA0)
+#define GPIO_INT_STATUS_1  GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2  GPIO1_REG(0xA4)
+#define GPIO_INT_STATUS_3  GPIO1_REG(0xA8)
+#define GPIO_INT_STATUS_4  GPIO1_REG(0xAC)
+#define GPIO_INT_STATUS_5  GPIO1_REG(0xB0)
+#define GPIO_INT_STATUS_6  GPIO1_REG(0xE0)
+#define GPIO_INT_STATUS_7  GPIO1_REG(0x234)
+
+
+#define GPIO_OUT_VAL_REG_BASE     0xABC00000
+#define GPIO_ALT_FUNC_PAGE_REG    (GPIO_OUT_VAL_REG_BASE + 0x20)
+#define GPIO_ALT_FUNC_CFG_REG     (GPIO_OUT_VAL_REG_BASE + 0x24)
+
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL    0
+#define GPIO_PULL_DOWN  1
+#define GPIO_KEEPER     2
+#define GPIO_PULL_UP    3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA        0
+#define GPIO_4MA        1
+#define GPIO_6MA        2
+#define GPIO_8MA        3
+#define GPIO_10MA       4
+#define GPIO_12MA       5
+#define GPIO_14MA       6
+#define GPIO_16MA       7
+
+#define GPIO38_GPIO_CNTRL      0x175
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE     0
+#define GPIO_DISABLE    1
+
+#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
+       ((((gpio) & 0x3FF) << 4)        |   \
+       ((func) & 0xf)                  |   \
+       (((dir) & 0x1) << 14)           |   \
+       (((pull) & 0x3) << 15)          |   \
+       (((drvstr) & 0xF) << 17))
+
+/**
+ * struct msm_gpio - GPIO pin description
+ * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
+ * @label - textual label
+ *
+ * Usually, GPIO's are operated by sets.
+ * This struct accumulate all GPIO information in single source
+ * and facilitete group operations provided by msm_gpios_xxx()
+ */
+struct msm_gpio {
+       unsigned gpio_cfg;
+       const char *label;
+};
+
+/**
+ * extract GPIO pin from bit-field used for gpio_tlmm_config
+ */
+#define GPIO_PIN(gpio_cfg)    (((gpio_cfg) >>  4) & 0x3ff)
+#define GPIO_FUNC(gpio_cfg)   (((gpio_cfg) >>  0) & 0xf)
+#define GPIO_DIR(gpio_cfg)    (((gpio_cfg) >> 14) & 0x1)
+#define GPIO_PULL(gpio_cfg)   (((gpio_cfg) >> 15) & 0x3)
+#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf)
+
+#endif
diff --git a/arch/arm/include/asm/arch-msm7630/iomap.h b/arch/arm/include/asm/arch-msm7630/iomap.h
new file mode 100644
index 0000000..186c6c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/iomap.h
@@ -0,0 +1,96 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __IOMAP_H_
+#define __IOMAP_H_
+
+#define MSM_UART1_BASE 0xACA00000
+#define MSM_UART2_BASE 0xACB00000
+#define MSM_UART3_BASE 0xACC00000
+
+#define MSM_VIC_BASE   0xC0080000
+#define MSM_TMR_BASE   0xC0100000
+
+#define MSM_GPT_BASE      (MSM_TMR_BASE + 0x04)
+#define MSM_DGT_BASE      (MSM_TMR_BASE + 0x24)
+#define SPSS_TIMER_STATUS (MSM_TMR_BASE + 0x88)
+
+#define GPT_REG(off)      (MSM_GPT_BASE + (off))
+#define DGT_REG(off)      (MSM_DGT_BASE + (off))
+
+#define GPT_MATCH_VAL      GPT_REG(0x0000)
+#define GPT_COUNT_VAL      GPT_REG(0x0004)
+#define GPT_ENABLE         GPT_REG(0x0008)
+#define GPT_CLEAR          GPT_REG(0x000C)
+
+#define DGT_MATCH_VAL      DGT_REG(0x0000)
+#define DGT_COUNT_VAL      DGT_REG(0x0004)
+#define DGT_ENABLE         DGT_REG(0x0008)
+#define DGT_CLEAR          DGT_REG(0x000C)
+#define DGT_CLK_CTL        DGT_REG(0x0010)
+
+#define HW_REVISION_NUMBER   0xABC00270
+
+#define MSM_CSR_BASE    0xC0100000
+#define MSM_GCC_BASE   0xC0182000
+
+#define MSM_SDC1_BASE   0xA0400000
+#define MSM_SDC2_BASE   0xA0500000
+#define MSM_SDC3_BASE   0xA3000000
+#define MSM_SDC4_BASE   0xA3100000
+
+#define MSM_SHARED_BASE      0x00100000
+#define MSM_CLK_CTL_BASE        0xAB800000
+#define MSM_CLK_CTL_SH2_BASE    0xABA01000
+
+#define REG_BASE(off)           (MSM_CLK_CTL_BASE + (off))
+#define REG_SH2_BASE(off)       (MSM_CLK_CTL_SH2_BASE + (off))
+
+#define SCSS_CLK_CTL            0xC0101004
+#define SCSS_CLK_SEL            0xC0101008
+
+#define MSM_USB_BASE                   0xA3600000
+#define MSM_CRYPTO_BASE                        0xA8400000
+
+#define SH2_USBH_MD_REG         REG_SH2_BASE(0x2BC)
+#define SH2_USBH_NS_REG         REG_SH2_BASE(0x2C0)
+
+#define SH2_MDP_NS_REG          REG_SH2_BASE(0x14C)
+#define SH2_MDP_LCDC_MD_REG     REG_SH2_BASE(0x38C)
+#define SH2_MDP_LCDC_NS_REG     REG_SH2_BASE(0x390)
+#define SH2_MDP_VSYNC_REG       REG_SH2_BASE(0x460)
+#define SH2_PMDH_NS_REG         REG_SH2_BASE(0x8C)
+
+#define SH2_GLBL_CLK_ENA_SC     REG_SH2_BASE(0x3BC)
+#define SH2_GLBL_CLK_ENA_2_SC   REG_SH2_BASE(0x3C0)
+
+#define SH2_OWN_ROW1_BASE_REG   REG_BASE(0x041C)
+#define SH2_OWN_ROW2_BASE_REG   REG_BASE(0x0424)
+#define SH2_OWN_APPS2_BASE_REG  REG_BASE(0x0414)
+
+#define MSM_ADM_BASE            0xAC200000
+#define MSM_ADM_SD_OFFSET       0x00100400
+
+#define MSM_SAW_BASE            0xC0102000
+
+#define PLL_ENA_REG             REG_SH2_BASE(0x0264)
+#define PLL2_STATUS_BASE_REG    REG_BASE(0x0350)
+#define PLL2_L_VAL_ADDR         REG_BASE(0x033C)
+#endif
diff --git a/arch/arm/include/asm/arch-msm7630/proc_comm.h b/arch/arm/include/asm/arch-msm7630/proc_comm.h
new file mode 100644
index 0000000..3df08b9
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/proc_comm.h
@@ -0,0 +1,42 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __PROC_COMM_H_
+#define __PROC_COMM_H_
+
+void usb_clock_init(void);
+void lcdc_clock_init(unsigned rate);
+void mdp_clock_init(unsigned rate);
+void uart3_clock_init(void);
+void uart2_clock_init(void);
+void uart1_clock_init(void);
+void mddi_clock_init(unsigned num, unsigned rate);
+void reboot(unsigned reboot_reason);
+int mmc_clock_enable_disable(unsigned id, unsigned enable);
+int mmc_clock_set_rate(unsigned id, unsigned rate);
+int mmc_clock_get_rate(unsigned id);
+int gpio_tlmm_config(unsigned config, unsigned disable);
+int vreg_set_level(unsigned id, unsigned mv);
+int vreg_enable(unsigned id);
+int vreg_disable(unsigned id);
+
+#endif
+
+
diff --git a/arch/arm/include/asm/arch-msm7630/sys_proto.h b/arch/arm/include/asm/arch-msm7630/sys_proto.h
new file mode 100644
index 0000000..c679d92
--- /dev/null
+++ b/arch/arm/include/asm/arch-msm7630/sys_proto.h
@@ -0,0 +1,29 @@ 
+/*
+ * (C) Copyright 2012
+ * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void pll8_enable(void);
+void clock_init(void);
+void __cpu_early_init(void);
+
+#endif
+