diff mbox

[U-Boot,v2] ARMV7: Add support For Logic OMAP35x/DM37x modules

Message ID 1323969301-4810-1-git-send-email-peter.barada@logicpd.com
State Changes Requested
Delegated to: Tom Rini
Headers show

Commit Message

Peter Barada Dec. 15, 2011, 5:15 p.m. UTC 
This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.


Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
Changes for V2:
    Rework logic_identify() into identify_board() - can't use checkboard()
    	   since its enabled by CONFIG_DISPLAY_BOARDINFO
    Properly indent comments in set_muxconf_regs()
    Move setup_net_chip() call from misc_init_r to board_eth_init()
    Remove triple empty line spacing
    Pass gpio_request(189) non-empty description
    Remove board/logicpd/omap3som/config.mk
    Remove clean/distclean from board/logicpd/omap3som/Makefile
    Modify board_mmc_init() to be one line function
    Modify include/configs/omap3_logic.h to use on/off #defines


 board/logicpd/omap3som/Makefile     |   42 +++
 board/logicpd/omap3som/omap3logic.c |  582 +++++++++++++++++++++++++++++++++++
 board/logicpd/omap3som/omap3logic.h |   35 ++
 boards.cfg                          |    1 +
 include/configs/omap3_logic.h       |  359 +++++++++++++++++++++
 5 files changed, 1019 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/omap3som/Makefile
 create mode 100644 board/logicpd/omap3som/omap3logic.c
 create mode 100644 board/logicpd/omap3som/omap3logic.h
 create mode 100644 include/configs/omap3_logic.h

Comments

Tom Rini Dec. 15, 2011, 6:30 p.m. UTC | #1 
On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.

#if 0'd code isn't allowed for merging so I assume this is an RFC :)

> +               /* Let it soak for a bit */
> +               for (i = 0; i < 0x100; ++i)
> +                       asm("nop");

Can we just use a sdelay(...) here?  And in the whole function you
haven't addressed Igor's comment (unless it's incoming and I just
haven't gotten the email yet) about this just being checkboard().

> +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> +#define LOGIC_NET_GPMC_CONFIG1  0x00001000
> +#define LOGIC_NET_GPMC_CONFIG2  0x00080801
> +#define LOGIC_NET_GPMC_CONFIG3  0x00000000
> +#define LOGIC_NET_GPMC_CONFIG4  0x08010801
> +#define LOGIC_NET_GPMC_CONFIG5  0x00080a0a
> +#define LOGIC_NET_GPMC_CONFIG6  0x03000280
> +#define LOGIC_NET_GPMC_CONFIG7  0x00000848
> +
> +/*
> + * Routine: setup_net_chip
> + * Description: Setting up the configuration GPMC registers specific to the
> + *             Ethernet hardware.
> + */
> +static void setup_net_chip(void)
> +{
> +       struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
> +
> +       /* Configure GPMC registers */
> +       writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
> +       writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
> +       writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
> +       writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
> +       writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
> +       writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
> +       writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
> +
> +       /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
> +       writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
> +       /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
> +       writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
> +       /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
> +       writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
> +               &ctrl_base->gpmc_nadv_ale);
> +
> +}

Or this just being an enable_gpmc_cs_config call.

> +int misc_init_r(void)
> +{
> +
> +       dieid_num_r();
> +
> +       return 0;
> +}

Extra whitespace.  I think checkpatch.pl will catch this so please run
your patch through checkpatch.pl, roughly like this:
$ git format-patch -1
$ ./tools/checkpatch.pl 0001-whatever-its-called.patch

[snip]
> +#define CONFIG_L2_OFF                  /* Keep L2 Cache Disabled */

Why do we want to do this?

[snip]
> +#define CONFIG_SYS_MAXARGS             64      /* max number of command args */

This is very very large and probably doesn't need to be.  This is the
number of arguments to the u-boot commands, not to the linux kernel.

Thanks.
Peter Barada Dec. 16, 2011, 6:09 a.m. UTC | #2 
On 12/15/2011 01:30 PM, Tom Rini wrote:
> On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>> reference boards. It assumes U-boot is loaded to SDRAM with the
>> help of another small bootloader (x-load) running from SRAM.
> #if 0'd code isn't allowed for merging so I assume this is an RFC :)
My bad - sent the wrong patch.  I'll update and send again.
>> +               /* Let it soak for a bit */
>> +               for (i = 0; i < 0x100; ++i)
>> +                       asm("nop");
> Can we just use a sdelay(...) here?  And in the whole function you
> haven't addressed Igor's comment (unless it's incoming and I just
> haven't gotten the email yet) about this just being checkboard().
Done - "sdelay(0x100)" instead of the delay loop.

As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
a checkboard() function that is called early (before relocation) that
prints out the banner.  I tried to make that a weak alias and override
it in my board file, but when its called, gd->bd is not setup so that
code aborts when it tries to set gd->bd->bi_arch_number.  I then tried
storing the value in a global and then set gd->bd->bi_arch_number in
board_init(), but between the call to checkboard() and board_init() the
BSS section is zeroed.  If I stored/load the computed bi_arch_number
into a non-zero static value it works, but I feel that is really fragile.

Remember that identify_board() not only prints a banner but also
determines one of four machine IDs passed to the linux kernel to
identify which of the variants its running on.

>> +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
>> +#define LOGIC_NET_GPMC_CONFIG1  0x00001000
>> +#define LOGIC_NET_GPMC_CONFIG2  0x00080801
>> +#define LOGIC_NET_GPMC_CONFIG3  0x00000000
>> +#define LOGIC_NET_GPMC_CONFIG4  0x08010801
>> +#define LOGIC_NET_GPMC_CONFIG5  0x00080a0a
>> +#define LOGIC_NET_GPMC_CONFIG6  0x03000280
>> +#define LOGIC_NET_GPMC_CONFIG7  0x00000848
>> +
>> +/*
>> + * Routine: setup_net_chip
>> + * Description: Setting up the configuration GPMC registers specific to the
>> + *             Ethernet hardware.
>> + */
>> +static void setup_net_chip(void)
>> +{
>> +       struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
>> +
>> +       /* Configure GPMC registers */
>> +       writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
>> +       writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
>> +       writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
>> +       writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
>> +       writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
>> +       writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
>> +       writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
>> +
>> +       /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
>> +       writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
>> +       /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
>> +       writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
>> +       /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
>> +       writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
>> +               &ctrl_base->gpmc_nadv_ale);
>> +
>> +}
> Or this just being an enable_gpmc_cs_config call.
Done.
>> +int misc_init_r(void)
>> +{
>> +
>> +       dieid_num_r();
>> +
>> +       return 0;
>> +}
> Extra whitespace.  I think checkpatch.pl will catch this so please run
> your patch through checkpatch.pl, roughly like this:
> $ git format-patch -1
> $ ./tools/checkpatch.pl 0001-whatever-its-called.patch
I rand checkpatch.pl over the result of "git diff --cached" and it
didn't complain about the emty line after the open brace.  I've removed it.
> [snip]
>> +#define CONFIG_L2_OFF                  /* Keep L2 Cache Disabled */
> Why do we want to do this?
This is a holdover from a previous verison ofu-boot (2010.06) where I
added LCD/HDMI support for up to a 720p 32bpp display and when I did
that the kernel wouldn't start w/o disabling L2 in u-boot (possibly
because the reserved memory for the display in u-boot alone is larger
than the L2 cache in a OMAP35x/DM37x), but I never figured out why it
failed.  I've removed it and will readdress when I add in the LCD/HDMI
support.

> [snip]
>> +#define CONFIG_SYS_MAXARGS             64      /* max number of command args */
> This is very very large and probably doesn't need to be.  This is the
> number of arguments to the u-boot commands, not to the linux kernel.
You're right, yet another holdover from an older version of u-boot. 
I've reduced it 16 to match up with most of the other boards.

So the big question before I submit V3 of this patch is whether to
include overriding OMAP3's checkboard() function or to use
identify_board() as is to compute bi_arch_number...  I can do it either
way, but don't want to waste anyone's time (with the wrong method).

Thanks in advance!
Tom Rini Dec. 16, 2011, 4:28 p.m. UTC | #3 
On Thu, Dec 15, 2011 at 11:09 PM, Peter Barada <peter.barada@logicpd.com> wrote:
> On 12/15/2011 01:30 PM, Tom Rini wrote:
>> On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
>>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>>> reference boards. It assumes U-boot is loaded to SDRAM with the
>>> help of another small bootloader (x-load) running from SRAM.
>> #if 0'd code isn't allowed for merging so I assume this is an RFC :)
> My bad - sent the wrong patch.  I'll update and send again.
>>> +               /* Let it soak for a bit */
>>> +               for (i = 0; i < 0x100; ++i)
>>> +                       asm("nop");
>> Can we just use a sdelay(...) here?  And in the whole function you
>> haven't addressed Igor's comment (unless it's incoming and I just
>> haven't gotten the email yet) about this just being checkboard().
> Done - "sdelay(0x100)" instead of the delay loop.

Great, thanks.

> As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
> a checkboard() function that is called early (before relocation) that
> prints out the banner.  I tried to make that a weak alias and override
> it in my board file, but when its called, gd->bd is not setup so that
> code aborts when it tries to set gd->bd->bi_arch_number.  I then tried
> storing the value in a global and then set gd->bd->bi_arch_number in
> board_init(), but between the call to checkboard() and board_init() the
> BSS section is zeroed.  If I stored/load the computed bi_arch_number
> into a non-zero static value it works, but I feel that is really fragile.
>
> Remember that identify_board() not only prints a banner but also
> determines one of four machine IDs passed to the linux kernel to
> identify which of the variants its running on.
[snip]
> So the big question before I submit V3 of this patch is whether to
> include overriding OMAP3's checkboard() function or to use
> identify_board() as is to compute bi_arch_number...  I can do it either
> way, but don't want to waste anyone's time (with the wrong method).

OK, after re-reading (and mentally applying the changes you said
you've got) the patches, along with Igor's comments on v1, just inline
your identify logic to board_init()
Igor Grinberg Dec. 18, 2011, 9 a.m. UTC | #4 
Hi Peter,

On 12/16/11 08:09, Peter Barada wrote:
> On 12/15/2011 01:30 PM, Tom Rini wrote:
>> On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
>>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>>> reference boards. It assumes U-boot is loaded to SDRAM with the
>>> help of another small bootloader (x-load) running from SRAM.

[...]

> As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
> a checkboard() function that is called early (before relocation) that
> prints out the banner.  I tried to make that a weak alias and override
> it in my board file, but when its called, gd->bd is not setup so that
> code aborts when it tries to set gd->bd->bi_arch_number.  I then tried
> storing the value in a global and then set gd->bd->bi_arch_number in
> board_init(), but between the call to checkboard() and board_init() the
> BSS section is zeroed.  If I stored/load the computed bi_arch_number
> into a non-zero static value it works, but I feel that is really fragile.

This make me wonder, should we move the checkboard() call further
in the init sequence?
Because, IIRC, it stayed in the same place, where it was, before
the relocation feature was introduced and board_init() was called
before the checkboard() (as board_init_f() does now).
Also, the struct bd_info (bd_t) should have the board data and
ironically it is not available in checkboard() function.

So, Albert, Wolfgang,
the question is, should we move the checkboard() call after
the gd->bd pointer initialization or are there any cases
where it is not appropriate?
Wolfgang Denk Dec. 18, 2011, 12:33 p.m. UTC | #5 
Dear Igor Grinberg,

In message <4EEDABA8.4010409@compulab.co.il> you wrote:
> 
> > As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
> > a checkboard() function that is called early (before relocation) that

And keep in mind: before relocation means that the BSS segment is not
available, and data segment is read-only.  [You may be lucky on some
systems that things appear to be different, but this is nothing you
should take granted, and it is definitely nothing that should be used
for common code.]

> > code aborts when it tries to set gd->bd->bi_arch_number.  I then tried
> > storing the value in a global and then set gd->bd->bi_arch_number in
> > board_init(), but between the call to checkboard() and board_init() the
> > BSS section is zeroed.  If I stored/load the computed bi_arch_number
> > into a non-zero static value it works, but I feel that is really fragile.

It is not only fragile, but broken.  See above: the data ssegment must
not be written before relocation.

> This make me wonder, should we move the checkboard() call further
> in the init sequence?

No, it should not.  It is part of the very early init code, and should
remain where it is.  Just don't add any code that does not belong
there.

> Also, the struct bd_info (bd_t) should have the board data and
> ironically it is not available in checkboard() function.

I don't see what is ironically about thaat.  bd_info does not exist at
that point of time.  You misinterpret the purpose of the checkboard()
function, it seems.

> So, Albert, Wolfgang,
> the question is, should we move the checkboard() call after
> the gd->bd pointer initialization or are there any cases
> where it is not appropriate?

Please leave as is, it is perfectly intentional.  Just don't place any
code in checkboard() which does not fit there.

Best regards,

Wolfgang Denk
diff mbox

Patch

diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
new file mode 100644
index 0000000..75e237b
--- /dev/null
+++ b/board/logicpd/omap3som/Makefile
@@ -0,0 +1,42 @@ 
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= omap3logic.o
+
+COBJS	:= $(sort $(COBJS-y))
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 0000000..0411adb
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,582 @@ 
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ *	Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "omap3logic.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Mux hsusb0_data5 as gpio_189 */
+#define MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX()				\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M4))
+
+/* Mux hsusb0_data5 as hasusb0_data5 */
+#define MUX_LOGIC_HSUSB0_DATA5_DATA5()					\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0))
+
+/* two dimensional array of Linux machine IDs; row it selected based on CPU,
+ * column is slected based on hsusb0_data5 having pulldown resistor */
+static struct board_id {
+	char *name;
+	int machine_id;
+} boards[2][2] = {
+	{
+		{
+			.name		= "OMAP35xx SOM LV",
+			.machine_id	= MACH_TYPE_OMAP3530_LV_SOM,
+		},
+		{
+			.name		= "OMAP35xx Torpedo",
+			.machine_id	= MACH_TYPE_OMAP3_TORPEDO,
+		},
+	},
+	{
+		{
+			.name		= "DM37xx SOM LV",
+			.machine_id	= MACH_TYPE_DM3730_SOM_LV,
+		},
+		{
+			.name		= "DM37xx Torpedo",
+			.machine_id	= MACH_TYPE_DM3730_TORPEDO,
+		},
+	},
+};
+
+/*
+ * Routine: identify_board
+ * Description: Detect if we are running on a Logic or Torpedo and which
+ *		variant (omap35x/dm37x).  Check gpio_189 - if its low after
+ *		driving it high, then its a SOM LV, else a Torpedo.
+ */
+static int identify_board(void)
+{
+	unsigned int val = 0;
+	u32 cpu_family = get_cpu_family();
+	int i;
+	struct board_id *board;
+
+	MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX();
+
+	if (gpio_request(189, "husb0_data5.gpio_189") == 0) {
+
+		gpio_direction_output(189, 0);
+		gpio_set_value(189, 1);
+
+		/* Let it soak for a bit */
+		for (i = 0; i < 0x100; ++i)
+			asm("nop");
+
+		gpio_direction_input(189);
+		val = gpio_get_value(189);
+		gpio_free(189);
+
+
+		board = &boards[!!(cpu_family == CPU_OMAP36XX)][!!val];
+
+		printf("Board: %s\n", board->name);
+		gd->bd->bi_arch_number = board->machine_id;
+
+#if 0
+		if (cpu_family == CPU_OMAP36XX) {
+			printf(" DM37xx");
+			if (val) {
+				printf(" Torpedo\n");
+				val = MACH_TYPE_DM3730_TORPEDO;
+			} else {
+				printf(" SOM LV\n");
+				val = MACH_TYPE_DM3730_SOM_LV;
+			}
+		} else {
+			printf(" OMAP35xx");
+			if (val) {
+				printf(" Torpedo\n");
+				val = MACH_TYPE_OMAP3_TORPEDO;
+			} else {
+				printf(" SOM LV\n");
+				val = MACH_TYPE_OMAP3530_LV_SOM;
+			}
+		}
+#endif
+	}
+
+	MUX_LOGIC_HSUSB0_DATA5_DATA5();
+
+
+	return 0;
+}
+
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+#define LOGIC_NET_GPMC_CONFIG1  0x00001000
+#define LOGIC_NET_GPMC_CONFIG2  0x00080801
+#define LOGIC_NET_GPMC_CONFIG3  0x00000000
+#define LOGIC_NET_GPMC_CONFIG4  0x08010801
+#define LOGIC_NET_GPMC_CONFIG5  0x00080a0a
+#define LOGIC_NET_GPMC_CONFIG6  0x03000280
+#define LOGIC_NET_GPMC_CONFIG7  0x00000848
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* Configure GPMC registers */
+	writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
+	writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
+	writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
+	writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
+	writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
+	writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
+	writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	/* Identify the board/cpu combination and set arch_number */
+	identify_board();
+
+	return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+
+	dieid_num_r();
+
+	return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+	setup_net_chip();
+
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	/*SDRC*/
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0));
+	/*GPMC*/
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M4));
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTU | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
+	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M7)); /*safe mode */
+	/*DSS*/
+	MUX_VAL(CP(DSS_PCLK),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_HSYNC),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_VSYNC),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_ACBIAS),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA0),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA1),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA2),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA3),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA4),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA5),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA6),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA7),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA8),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA9),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA10),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA11),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA12),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA13),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA14),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA15),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA16),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA17),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA18),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA19),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA20),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA21),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA22),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(DSS_DATA23),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	/*CAMERA*/
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_XCLKA),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_FLD),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_XCLKB),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CAM_STROBE),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	/*Audio Interface */
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(MCBSP2_DX),		(IEN  | PTD | EN  | M7)); /*safe mode */
+
+	/*Expansion card  */
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	/*Wireless LAN */
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	/*Bluetooth*/
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	/*Modem Interface */
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | EN  | M7)); /*safe mode*/
+
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP1_FSR),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP1_DX),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	/*Serial Interface*/
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(UART3_RTS_SD),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(UART3_TX_IRTX),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_STP),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0));
+
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M7)); /*safe mode*/
+	/*Control and debug */
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTD | EN  | M7)); /*safe mode */
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0));
+	/*Die to Die */
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)); /*safe mode*/
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 0000000..5b2ca66
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,35 @@ 
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"Logic DM37x/OMAP35x reference board",
+	"NAND",
+};
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e5b3e0..f07ae28 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -202,6 +202,7 @@  igep0030                     arm         armv7       igep0030            isee
 am3517_evm                   arm         armv7       am3517evm           logicpd        omap3
 omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
 omap3_zoom2                  arm         armv7       zoom2               logicpd        omap3
+omap3_logic                  arm         armv7       omap3som            logicpd        omap3
 omap3_mvblx                  arm         armv7       mvblx               matrix_vision  omap3
 am3517_crane                 arm         armv7       am3517crane         ti             omap3
 omap3_beagle                 arm         armv7       beagle              ti             omap3
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
new file mode 100644
index 0000000..3ab4edb
--- /dev/null
+++ b/include/configs/omap3_logic.h
@@ -0,0 +1,359 @@ 
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ *	Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#if 0
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
+#endif
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+#if 0
+#define CONFIG_OMAP3430		1	/* which is in a 35x/37x */
+#endif
+#define CONFIG_OMAP3_LOGIC		/* working with Logic OMAP boards */
+
+#undef CONFIG_USE_IRQ			/* no support for IRQs */
+
+#define CONFIG_SYS_TEXT_BASE	0x80400000
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R		/* misc_init_r dumps the die id */
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_CMDLINE_EDITING			/* cmd line edit/history */
+#define CONFIG_ZERO_BOOTDELAY_CHECK		/* check keypress w/no delay */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			1	/* UART1 on OMAP Logic boards */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(x-loader),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
+#define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SETECPR	/* Evaluate expressions		*/
+
+#define CONFIG_L2_OFF			/* Keep L2 Cache Disabled */
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_I2C_MULTI_BUS		1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		2
+
+#define CONFIG_PREBOOT \
+	"echo ======================NOTICE============================;"\
+	"echo The u-boot environment is not set. - You are;"            \
+	"echo required to set a valid display for your LCD panel.;"	\
+	"echo Valid display options are:;"				\
+	"echo \"  2 == LQ121S1DG31     TFT SVGA    (12.1)  Sharp\";"	\
+	"echo \"  3 == LQ036Q1DA01     TFT QVGA    (3.6)   Sharp w/ASIC\";" \
+	"echo \"  5 == LQ064D343       TFT VGA     (6.4)   Sharp\";"	\
+	"echo \"  7 == LQ10D368        TFT VGA     (10.4)  Sharp\";"	\
+	"echo \" 15 == LQ043T1DG01     TFT WQVGA   (4.3)   Sharp (DEFAULT)\";" \
+	"echo \" vga[-16 OR -24]       LCD VGA     640x480\";"          \
+	"echo \" svga[-16 OR -24]      LCD SVGA    800x600\";"          \
+	"echo \" xga[-16 OR -24]       LCD XGA     1024x768\";"         \
+	"echo \" 720p[-16 OR -24]      LCD 720P    1280x720\";"         \
+	"echo \" sxga[-16 OR -24]      LCD SXGA    1280x1024\";"        \
+	"echo \" uxga[-16 OR -24]      LCD UXGA    1600x1200\";"        \
+	"echo MAKE SURE YOUR DISPLAY VARIABLE IS CORRECTLY ENTERED!;"	\
+	"setenv display 15;"						\
+	"setenv preboot;"						\
+	"saveenv;"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x81000000\0" \
+	"bootfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mmcdev=0\0" \
+	"autoboot=if mmc rescan ${mmcdev}; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"run defaultboot;" \
+			"fi; " \
+		"else run defaultboot; fi\0" \
+	"defaultboot=run mmcramboot\0" \
+	"consoledevice=ttyO0\0" \
+	"display=15\0" \
+	"setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+	"dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+	"rotation=0\0" \
+	"vrfb_arg=if itest ${rotation} -ne 0; then " \
+		"setenv bootargs ${bootargs} omapfb.vrfb=y " \
+		"omapfb.rotate=${rotation}; " \
+		"fi\0" \
+	"otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+	"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+		"${otherbootargs};" \
+		"run addmtdparts; " \
+		"run vrfb_arg\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo 'Running bootscript from mmc ...'; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=mmc rescan ${mmcdev}; " \
+		"fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"ramdisksize=64000\0" \
+	"ramdiskaddr=0x82000000\0" \
+	"ramdiskimage=rootfs.ext2.gz.uboot\0" \
+	"ramargs=run setconsole; setenv bootargs console=${console} " \
+		"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+	"mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+		"run ramargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"run loaduimage; " \
+		"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+		"bootm ${loadaddr} ${ramdiskaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run autoboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"OMAP Logic # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		64	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#endif
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE	0x08000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+
+#endif /* __CONFIG_H */