| Message ID | 20200320133452.3705040-2-thierry.reding@gmail.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | clocksource: Add NVIDIA Tegra186 timers support | expand |
On Fri, Mar 20, 2020 at 02:34:46PM +0100, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The NVIDIA Tegra186 SoC contains an IP block that provides a register > interface for ten timers with a 29-bit counter that can generate one- > shot, periodic or watchdog interrupts. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > .../bindings/timer/nvidia,tegra186-timer.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > > diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > new file mode 100644 > index 000000000000..f9b55041a5ca > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra186 timers > + > +maintainers: > + - Thierry Reding <thierry.reding@gmail.com> > + - Jonathan Hunter <jonathanh@nvidia.com> > + > +description: | > + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC > + (timestamp counter). The timers run at either a fixed 1 MHz clock rate > + derived from the oscillator clock. Each timer can be programmed to raise > + one-shot, periodic, or watchdog interrupts. > + > +properties: > + compatible: > + oneOf: > + - description: NVIDIA Tegra186 > + items: > + - const: nvidia,tegra186-timer > + > + - description: NVIDIA Tegra194 > + items: > + - const: nvidia,tegra194-timer > + - const: nvidia,tegra186-timer > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 10 required props? Also, add: additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + timer@3010000 { > + compatible = "nvidia,tegra186-timer"; > + reg = <0x03010000 0x000e0000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; Don't show status in examples. > + }; > -- > 2.24.1 >
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml new file mode 100644 index 000000000000..f9b55041a5ca --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 timers + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +description: | + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC + (timestamp counter). The timers run at either a fixed 1 MHz clock rate + derived from the oscillator clock. Each timer can be programmed to raise + one-shot, periodic, or watchdog interrupts. + +properties: + compatible: + oneOf: + - description: NVIDIA Tegra186 + items: + - const: nvidia,tegra186-timer + + - description: NVIDIA Tegra194 + items: + - const: nvidia,tegra194-timer + - const: nvidia,tegra186-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 10 + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };