From patchwork Fri Mar 20 13:34:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1258914 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Db5vCvVX; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48kPtH3P67z9sT4 for ; Sat, 21 Mar 2020 00:35:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727415AbgCTNfG (ORCPT ); Fri, 20 Mar 2020 09:35:06 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:40959 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727400AbgCTNfG (ORCPT ); Fri, 20 Mar 2020 09:35:06 -0400 Received: by mail-wr1-f66.google.com with SMTP id f3so7478591wrw.7; Fri, 20 Mar 2020 06:35:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ADXJiGCDvrv56l+ieUm/SAdymbh3Yub2i9bAMUxwsik=; b=Db5vCvVX3kdDDG4TWQ8K/qx0s58cL0uzjYWQQmQTNfhrKnN21Q7JfcSVcOHBO9DvvT 8GtzJL3B98vqCSPLQVyf5XXk/obGzEtkLVgtMrwKgA/o8OK6Gp6gQZ/+zk3VCbj2iPlp WhefUdDx9INTUnwRmkNK/kJjn/aGSszGNZsQPPjbTIbkYgG9LSwKBA+IIwIBkSsDv7oH QmaqGTpi+xyKgha+bxzMQ0QUk78LI3ZX3ogmR1JY7K55sO08YrnWZ2jL8UHo2Z9ESKWe v9j44atOsFMmnz8YgW6rd65wfjQ6Muf9VPLO6KoX0EFa+U3KdtkZC+SpQ75SS3xB1z8m OMIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ADXJiGCDvrv56l+ieUm/SAdymbh3Yub2i9bAMUxwsik=; b=oXLjnsvLH5069hf+/ZSOUX7KqMlweazw2gIu1k4K+8M1SzuJZwszwGlq59Wfu0PKgT REpu+uXfjuQFh/MYPYqaSdvdRSOzKgqVEcxapORXaYo/yIN27FjKka69F7oPuH/N+ZOH Re2TAB+etnWunIJuiLHl4ktc3kdOl+0szAEEuKS7sLcAAq9fzQC5F9HWLLC8iGFvLOkZ EGYoVJehJV7ZvgSbvQYFqoZ1FkDjGfsNftQGe2qg+BrvcdH9RbTh5I14whtGQSe2NKfT QJD9zpvbl3IqZcTSrS3oehC54yl3TL1G8FpFwwdkijunht5Z2jlDqVawxcxg1c1jOvZI Me0Q== X-Gm-Message-State: ANhLgQ2UX3FE9QTmqMwqNMJOqdOzFenF30A9TrFvEHTCkrvdxEBejNqX bKpbWBF4OQUJcEy4T1DqzE0= X-Google-Smtp-Source: ADFU+vuqshN9lSmln+18D87rL++S+Fb8k19lx7heUddfv7aKn737EG+IaVZYk9R/pOva1OhAL3A7bw== X-Received: by 2002:adf:e98a:: with SMTP id h10mr202766wrm.370.1584711304489; Fri, 20 Mar 2020 06:35:04 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id g14sm7963218wme.32.2020.03.20.06.35.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 06:35:03 -0700 (PDT) From: Thierry Reding To: Thomas Gleixner , Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: timer: Add bindings for NVIDIA Tegra186 timers Date: Fri, 20 Mar 2020 14:34:46 +0100 Message-Id: <20200320133452.3705040-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200320133452.3705040-1-thierry.reding@gmail.com> References: <20200320133452.3705040-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The NVIDIA Tegra186 SoC contains an IP block that provides a register interface for ten timers with a 29-bit counter that can generate one- shot, periodic or watchdog interrupts. Signed-off-by: Thierry Reding --- .../bindings/timer/nvidia,tegra186-timer.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml new file mode 100644 index 000000000000..f9b55041a5ca --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 timers + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: | + The Tegra186 timer provides ten 29-bit timer counters and one 32-bit TSC + (timestamp counter). The timers run at either a fixed 1 MHz clock rate + derived from the oscillator clock. Each timer can be programmed to raise + one-shot, periodic, or watchdog interrupts. + +properties: + compatible: + oneOf: + - description: NVIDIA Tegra186 + items: + - const: nvidia,tegra186-timer + + - description: NVIDIA Tegra194 + items: + - const: nvidia,tegra194-timer + - const: nvidia,tegra186-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 10 + +examples: + - | + #include + + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; From patchwork Fri Mar 20 13:34:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1258913 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=p19SPgPe; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48kPtB2Vnyz9sSt for ; Sat, 21 Mar 2020 00:35:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727191AbgCTNfp (ORCPT ); Fri, 20 Mar 2020 09:35:45 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:38549 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727421AbgCTNfI (ORCPT ); Fri, 20 Mar 2020 09:35:08 -0400 Received: by mail-wm1-f68.google.com with SMTP id l20so6352026wmi.3; Fri, 20 Mar 2020 06:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u5cvJnNy7rAzr+MR1scINKdcIp3JWPdrNsZ6zcMIVv4=; b=p19SPgPejGnTVvwBAFp6mGqj9G09TyJAC5X2QImlRQopPKDsfqINnD4PyGN0oHvzoP Sb6W07fXufM161Sk9P6T5suaFfwY5h0Yth+apytQanDyhuGom6wf5bMK1Ukb5sMi6Mhs 1IONjXqOQzoahXd4kV94p0tlfW+x2ewnVEFGUWF+WAmxifl7EfnCWU6Pq9HmYKhVe6Z4 uB7STSa4MY8c5quhpV+hAZ7agaJlmGOHLz72FzC+f4i4pn5nIbX4CYHPODZ1/fsDiB97 LlY0FFtM5toQVc2/iKt+QcjSLff7bUixJ1KenSwx4VHu+QnEmtFgVqI8kFlJkvmdjKh0 brrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u5cvJnNy7rAzr+MR1scINKdcIp3JWPdrNsZ6zcMIVv4=; b=a5e97drkhjxzTRz3AqdiNns2ke9OT57tDdHbhH8NEZJENFD4/67i3J1KYxMA5k7T2k WNrqbADNrE25yOFfdnIRAxIhfK9afrGZ39keBvMYW397okW9NGaSzjbMvFV+uRx1O4rd lYI0Ov2/eQde4heyVkbJ2Aj4R6L94kQLVWC5DPDyjDujQIk9nNCzS53KR4iFA2BXvzc9 2c6S36iuDy1JvE2iAdTQXyUwpvG6t6QjgRp09JWcsmDE5yQJlHx+YAXHwaE7eko5MD7z C5FC1fU5/DeApTQG5N/RlZSBS/qBs0YZrbtjqOQHuTd6tXZMPYyt7TG+eDckSHNA0SKy s1lg== X-Gm-Message-State: ANhLgQ27EcxbbNQT/ToI5/PqchRpuTOLK4kkMYT3yZlQS5AgOvLmmiO1 Y0QYYLQWopRUblwBrPErNhQ= X-Google-Smtp-Source: ADFU+vtf+LzzSJ8so+tDHns/2cSauccKBJ/XdHAkB3Gr0pIdrtAlho2CPDyKdeFvEYM04ty9UQBu3A== X-Received: by 2002:a7b:c208:: with SMTP id x8mr10223733wmi.136.1584711306228; Fri, 20 Mar 2020 06:35:06 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id f15sm8409248wru.83.2020.03.20.06.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 06:35:05 -0700 (PDT) From: Thierry Reding To: Thomas Gleixner , Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] clocksource: Add Tegra186 timers support Date: Fri, 20 Mar 2020 14:34:47 +0100 Message-Id: <20200320133452.3705040-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200320133452.3705040-1-thierry.reding@gmail.com> References: <20200320133452.3705040-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Currently this only supports a single watchdog, which uses a timer in the background for countdown. Eventually the timers could be used for various time-keeping tasks, but by default the architected timer will already provide that functionality. Signed-off-by: Thierry Reding --- drivers/clocksource/Kconfig | 8 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-tegra186.c | 377 +++++++++++++++++++++++++++ 3 files changed, 386 insertions(+) create mode 100644 drivers/clocksource/timer-tegra186.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index f2142e6bbea3..54d1b27d1f8b 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -149,6 +149,14 @@ config TEGRA_TIMER help Enables support for the Tegra driver. +config TEGRA186_TIMER + bool "NVIDIA Tegra186 timer driver" + depends on ARCH_TEGRA || COMPILE_TEST + select TIMER_OF + help + Enables support for the timers and watchdogs found on NVIDIA + Tegra186 and later SoCs. + config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 641ba5383ab5..ffa7950f4b7c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra.o +obj-$(CONFIG_TEGRA186_TIMER) += timer-tegra186.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c new file mode 100644 index 000000000000..f8bdda041e3a --- /dev/null +++ b/drivers/clocksource/timer-tegra186.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* shared registers */ +#define TKEIE(x) (0x100 + ((x) * 4)) +#define TKEIE_WDT_MASK(x, y) ((y) << (16 + 4 * (x))) + +/* timer registers */ +#define TMRCR 0x000 +#define TMRCR_ENABLE BIT(31) +#define TMRCR_PERIODIC BIT(30) +#define TMRCR_PTV(x) ((x) & 0x0fffffff) + +#define TMRSR 0x004 +#define TMRSR_INTR_CLR BIT(30) + +#define TMRCSSR 0x008 +#define TMRCSSR_SRC_USEC (0 << 0) + +/* watchdog registers */ +#define WDTCR 0x000 +#define WDTCR_SYSTEM_POR_RESET_ENABLE BIT(16) +#define WDTCR_SYSTEM_DEBUG_RESET_ENABLE BIT(15) +#define WDTCR_REMOTE_INT_ENABLE BIT(14) +#define WDTCR_LOCAL_FIQ_ENABLE BIT(13) +#define WDTCR_LOCAL_INT_ENABLE BIT(12) +#define WDTCR_PERIOD_MASK (0xff << 4) +#define WDTCR_PERIOD(x) (((x) & 0xff) << 4) +#define WDTCR_TIMER_SOURCE_MASK 0xf +#define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) + +#define WDTCMDR 0x008 +#define WDTCMDR_DISABLE_COUNTER BIT(1) +#define WDTCMDR_START_COUNTER BIT(0) + +#define WDTUR 0x00c +#define WDTUR_UNLOCK_PATTERN 0x0000c45a + +struct tegra186_timer_soc { + unsigned int num_timers; + unsigned int num_wdts; +}; + +struct tegra186_tmr { + struct tegra186_timer *parent; + void __iomem *regs; + unsigned int index; + unsigned int hwirq; +}; + +struct tegra186_wdt { + struct watchdog_device base; + + void __iomem *regs; + unsigned int index; + bool locked; + + struct tegra186_tmr *tmr; +}; + +static inline struct tegra186_wdt *to_tegra186_wdt(struct watchdog_device *wdd) +{ + return container_of(wdd, struct tegra186_wdt, base); +} + +struct tegra186_timer { + const struct tegra186_timer_soc *soc; + struct device *dev; + void __iomem *regs; + unsigned int irq; + + struct tegra186_wdt *wdt; +}; + +static void tmr_writel(struct tegra186_tmr *tmr, u32 value, unsigned int offset) +{ + writel(value, tmr->regs + offset); +} + +static void wdt_writel(struct tegra186_wdt *wdt, u32 value, unsigned int offset) +{ + writel(value, wdt->regs + offset); +} + +static u32 wdt_readl(struct tegra186_wdt *wdt, unsigned int offset) +{ + return readl(wdt->regs + offset); +} + +static struct tegra186_tmr *tegra186_tmr_create(struct tegra186_timer *tegra, + unsigned int index) +{ + unsigned int offset = 0x10000 + index * 0x10000; + struct tegra186_tmr *tmr; + + tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); + if (!tmr) + return ERR_PTR(-ENOMEM); + + tmr->parent = tegra; + tmr->regs = tegra->regs + offset; + tmr->index = index; + tmr->hwirq = 0; + + return tmr; +} + +static const struct watchdog_info tegra186_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, + .identity = "NVIDIA Tegra186 WDT", +}; + +static void tegra186_wdt_disable(struct tegra186_wdt *wdt) +{ + /* unlock and disable the watchdog */ + wdt_writel(wdt, WDTUR_UNLOCK_PATTERN, WDTUR); + wdt_writel(wdt, WDTCMDR_DISABLE_COUNTER, WDTCMDR); + + /* disable timer */ + tmr_writel(wdt->tmr, 0, TMRCR); +} + +static void tegra186_wdt_enable(struct tegra186_wdt *wdt) +{ + struct tegra186_timer *tegra = wdt->tmr->parent; + u32 value; + + /* unmask hardware IRQ, this may have been lost across powergate */ + value = TKEIE_WDT_MASK(wdt->index, 1); + writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq)); + + /* clear interrupt */ + tmr_writel(wdt->tmr, TMRSR_INTR_CLR, TMRSR); + + /* select microsecond source */ + tmr_writel(wdt->tmr, TMRCSSR_SRC_USEC, TMRCSSR); + + /* configure timer (system reset happens on the fifth expiration) */ + value = TMRCR_PTV(wdt->base.timeout * USEC_PER_SEC / 5) | + TMRCR_PERIODIC | TMRCR_ENABLE; + tmr_writel(wdt->tmr, value, TMRCR); + + if (!wdt->locked) { + value = wdt_readl(wdt, WDTCR); + + /* select the proper timer source */ + value &= ~WDTCR_TIMER_SOURCE_MASK; + value |= WDTCR_TIMER_SOURCE(wdt->tmr->index); + + /* single timer period since that's already configured */ + value &= ~WDTCR_PERIOD_MASK; + value |= WDTCR_PERIOD(1); + + /* enable local interrupt for WDT petting */ + value |= WDTCR_LOCAL_INT_ENABLE; + + /* enable local FIQ and remote interrupt for debug dump */ + if (0) + value |= WDTCR_REMOTE_INT_ENABLE | + WDTCR_LOCAL_FIQ_ENABLE; + + /* enable system debug reset (doesn't properly reboot) */ + if (0) + value |= WDTCR_SYSTEM_DEBUG_RESET_ENABLE; + + /* enable system POR reset */ + value |= WDTCR_SYSTEM_POR_RESET_ENABLE; + + wdt_writel(wdt, value, WDTCR); + } + + wdt_writel(wdt, WDTCMDR_START_COUNTER, WDTCMDR); +} + +static int tegra186_wdt_start(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + tegra186_wdt_enable(wdt); + + return 0; +} + +static int tegra186_wdt_stop(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + tegra186_wdt_disable(wdt); + + return 0; +} + +static int tegra186_wdt_ping(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + tegra186_wdt_disable(wdt); + tegra186_wdt_enable(wdt); + + return 0; +} + +static int tegra186_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) +{ + struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); + + tegra186_wdt_disable(wdt); + wdt->base.timeout = timeout; + tegra186_wdt_enable(wdt); + + return 0; +} + +static const struct watchdog_ops tegra186_wdt_ops = { + .owner = THIS_MODULE, + .start = tegra186_wdt_start, + .stop = tegra186_wdt_stop, + .ping = tegra186_wdt_ping, + .set_timeout = tegra186_wdt_set_timeout, +}; + +static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra, + unsigned int index) +{ + unsigned int offset = 0x10000, source; + struct tegra186_wdt *wdt; + u32 value; + int err; + + offset += tegra->soc->num_timers * 0x10000 + index * 0x10000; + + wdt = devm_kzalloc(tegra->dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return ERR_PTR(-ENOMEM); + + wdt->regs = tegra->regs + offset; + wdt->index = index; + + /* read the watchdog configuration since it might be locked down */ + value = wdt_readl(wdt, WDTCR); + + if (value & WDTCR_LOCAL_INT_ENABLE) + wdt->locked = true; + + source = value & WDTCR_TIMER_SOURCE_MASK; + + wdt->tmr = tegra186_tmr_create(tegra, source); + if (IS_ERR(wdt->tmr)) + return ERR_CAST(wdt->tmr); + + wdt->base.info = &tegra186_wdt_info; + wdt->base.ops = &tegra186_wdt_ops; + wdt->base.min_timeout = 1; + wdt->base.max_timeout = 255; + wdt->base.parent = tegra->dev; + + err = watchdog_init_timeout(&wdt->base, 5, tegra->dev); + if (err < 0) { + dev_err(tegra->dev, "failed to initialize timeout: %d\n", err); + return ERR_PTR(err); + } + + err = devm_watchdog_register_device(tegra->dev, &wdt->base); + if (err < 0) { + dev_err(tegra->dev, "failed to register WDT: %d\n", err); + return ERR_PTR(err); + } + + return wdt; +} + +static irqreturn_t tegra186_timer_irq(int irq, void *data) +{ + struct tegra186_timer *tegra = data; + + if (tegra->wdt) { + tegra186_wdt_disable(tegra->wdt); + tegra186_wdt_enable(tegra->wdt); + } + + return IRQ_HANDLED; +} + +static int tegra186_timer_probe(struct platform_device *pdev) +{ + struct tegra186_timer *tegra; + int err; + + tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); + if (!tegra) + return -ENOMEM; + + tegra->soc = of_device_get_match_data(&pdev->dev); + dev_set_drvdata(&pdev->dev, tegra); + tegra->dev = &pdev->dev; + + tegra->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tegra->regs)) + return PTR_ERR(tegra->regs); + + err = platform_get_irq(pdev, 0); + if (err < 0) { + dev_err(tegra->dev, "failed to get interrupt #0: %d\n", err); + return err; + } + + tegra->irq = err; + + err = devm_request_irq(tegra->dev, tegra->irq, tegra186_timer_irq, + IRQF_ONESHOT | IRQF_TRIGGER_HIGH, + "tegra186-timer", tegra); + if (err < 0) { + dev_err(tegra->dev, "failed to request IRQ#%u: %d\n", + tegra->irq, err); + return err; + } + + /* create a watchdog using a preconfigured timer */ + tegra->wdt = tegra186_wdt_create(tegra, 0); + if (IS_ERR(tegra->wdt)) { + err = PTR_ERR(tegra->wdt); + dev_err(&pdev->dev, "failed to create WDT: %d\n", err); + return err; + } + + return 0; +} + +static int __maybe_unused tegra186_timer_suspend(struct device *dev) +{ + return 0; +} + +static int __maybe_unused tegra186_timer_resume(struct device *dev) +{ + return 0; +} + +static SIMPLE_DEV_PM_OPS(tegra186_timer_pm_ops, tegra186_timer_suspend, + tegra186_timer_resume); + +static const struct tegra186_timer_soc tegra186_timer = { + .num_timers = 10, + .num_wdts = 3, +}; + +static const struct of_device_id tegra186_timer_of_match[] = { + { .compatible = "nvidia,tegra186-timer", .data = &tegra186_timer }, + { } +}; + +static struct platform_driver tegra186_wdt_driver = { + .driver = { + .name = "tegra186-timer", + .pm = &tegra186_timer_pm_ops, + .of_match_table = tegra186_timer_of_match, + .suppress_bind_attrs = true, + }, + .probe = tegra186_timer_probe, +}; +module_platform_driver(tegra186_wdt_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra186 timers driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Mar 20 13:34:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1258906 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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[217.229.28.220]) by smtp.gmail.com with ESMTPSA id s22sm7160030wmc.16.2020.03.20.06.35.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 06:35:09 -0700 (PDT) From: Thierry Reding To: Thomas Gleixner , Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] arm64: tegra: Add native timer support on Tegra186 Date: Fri, 20 Mar 2020 14:34:49 +0100 Message-Id: <20200320133452.3705040-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200320133452.3705040-1-thierry.reding@gmail.com> References: <20200320133452.3705040-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58100fb9cd8b..4dfa70e93693 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -167,6 +167,22 @@ emc: external-memory-controller@2c60000 { }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; From patchwork Fri Mar 20 13:34:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1258911 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=bYiSWXG8; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48kPt349Xcz9sSX for ; Sat, 21 Mar 2020 00:35:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727561AbgCTNfe (ORCPT ); Fri, 20 Mar 2020 09:35:34 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:52830 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727471AbgCTNfO (ORCPT ); Fri, 20 Mar 2020 09:35:14 -0400 Received: by mail-wm1-f68.google.com with SMTP id 11so6533689wmo.2; Fri, 20 Mar 2020 06:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ie6jFqOSrTu+xf/V4MNbj7GzVLme0az5kv4/5mQNB0k=; b=bYiSWXG8HNjZu608MUAN1KPB+00ESgXXtFJe3GhMQamj1oqGRLdIag3YlPDV84IXVx Pk2IKG85pzwF+e2b1gPFFZP1XlJMDBM1eOJozEl3FYERUxf42zq8cNoXdifXXmFSZUIm s3QvzOLmDGB7sdRpYfXUOXxBnk/TKAmHkuQLNxDD0jZO0vBcu5w4IWQmJZr9hJ3ZqgOh XVJ7CVyUYtY4PtZSDFVsRTp3sLEV68KxruuIpNGs6o2eA14en3bYLw0YRCr/0F/s4NOL PmLGJsdYO2Q1CKNTDho+GzRMnNeXIOmXyqakuaFBnV1DfMxJsME7EDYWKbfBBQTKD85a Se6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ie6jFqOSrTu+xf/V4MNbj7GzVLme0az5kv4/5mQNB0k=; b=gHujxYpJsKYNvJNcZ05UyHp3wG6N9oysZV3mG+8qotCYzT04k+MbwOlakTtrRKJbgY iebcQj6h+FkQHmraAdcHeSqwZdP55ImOO6jpPUTMy9h+lspIzorseHQCAF99Hm+zonrB ETDVlp5OD5o6cxmK5I4CoAygQDgMAX9l7rdYvtHVcXCiyK0zhDMVvcTwTGelZf7/UP2d T1qUd19t3yyuuoxXJLo1yK32QNlG+acG6X4X4tSphbr2I9yChVGcG8agnHJVzghSaJcI fcpd1aCu7rIxtAonHtAh7pqeHQzY6qbZ2zKAa6AfPuRBG4YhCN3fUN+dAaBZZrFep+6k bkEw== X-Gm-Message-State: ANhLgQ3Wl/0FQmCkirqYAPCO2kTi9kYxVtyb9sBgWtwsJZ9m3mHu7y4D wlYm80jRYEUK6Dy+XRK8xlY= X-Google-Smtp-Source: ADFU+vsxJ/OjFy5JkjSacUfjpV9FUE3JNkijj7IBK0oDz5QHO52DdVAXkWTcM1oGmUpgb0A5Bptssw== X-Received: by 2002:a1c:68d5:: with SMTP id d204mr10231998wmc.15.1584711312059; Fri, 20 Mar 2020 06:35:12 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id j39sm8892844wre.11.2020.03.20.06.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 06:35:11 -0700 (PDT) From: Thierry Reding To: Thomas Gleixner , Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] arm64: tegra: Enable native timers on Jetson TX2 Date: Fri, 20 Mar 2020 14:34:50 +0100 Message-Id: <20200320133452.3705040-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200320133452.3705040-1-thierry.reding@gmail.com> References: <20200320133452.3705040-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Enable the native timers on Jetson TX2 to allow using the watchdog functionality to recover from system hangs, for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index da96de04d003..9aa17744c4a0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -58,6 +58,10 @@ memory-controller@2c00000 { status = "okay"; }; + timer@3010000 { + status = "okay"; + }; + serial@3100000 { status = "okay"; }; From patchwork Fri Mar 20 13:34:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1258909 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=XDDOZzd5; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48kPsx2bvcz9sSm for ; Sat, 21 Mar 2020 00:35:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727507AbgCTNfQ (ORCPT ); Fri, 20 Mar 2020 09:35:16 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:34110 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727490AbgCTNfP (ORCPT ); Fri, 20 Mar 2020 09:35:15 -0400 Received: by mail-wm1-f68.google.com with SMTP id 26so3049726wmk.1; Fri, 20 Mar 2020 06:35:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WS2drkVzUywPkUAraDwxibChKAzL4Ioj5dgxbparViM=; b=XDDOZzd5oKgpObDjVSEymgFC00jnB6CJGgwYRpLe2YS56tTaQuoAwzkFzt2ONA3MAh oScRa2rjuEALTd3sH8oQ0p0FYExZ0MS/yjTjQgoR7sfcRbWo/luQwsR9vu8O1cI9rgq7 xdD8+oNHLyo3ziH20YvKtD4/wPNTF91ywgEutQ/og6+syfumauw0xTDTmjf7j7I2A3Fa /sJ8pVDYUJSbLqp2nGfmeVYSJs8f5uU9n3Sjojy1EqznPwhjMgVTXVg5rGDgcBk+NUq5 rMZihxPy7DYyM7HdGztCmqSbYuhZd7o1yGX/BcHyoyDGWzNx8AQXUBv5uQR8rnkHSLtd yVBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WS2drkVzUywPkUAraDwxibChKAzL4Ioj5dgxbparViM=; b=G9uadDJhB5o3KA1gpH+v14UDjHQSZ1UU4cgd5V2qs/5w7UD/YddT/og5Ya1IwpTDN9 dttdyVDsPZi8ufjY4GpWy3sqLpIZ9Aj1mwnrwcvqvhJOoQVa18REtrlVX+/mb8UD6ozm hADYQjsev8VJFJnUMKu3FhmtNNw990aO6EDIEJ0ZOt2rvlOfqkoqhKhIAdn6udbe5ia+ G3/iGaHLDRqVwXb2xdXuS694ZXyuGjRhKKVJqLnL1wUZuIfxyHkP+Ox3GxkAIDhhnLLu DOLMbUlYjLl3qVl7v7pTmT/e/9kHHoJCpLvg6sIVvAOR7L2BER6ebA5+kPhxGA+VUdQi 1cpw== X-Gm-Message-State: ANhLgQ1WqKtUGqpIuSQgwLL9lbnD6YJTNN5k62Ylr37p7dyqzZQiFERg pqUqcVeOm1iyWxcOPou3ZXU= X-Google-Smtp-Source: ADFU+vu4Jujmu4QzXEDeYZvm3w3yoKNfvuqOg7RHd7k31B8z5CPlT0KxTW1WbrEw48Wc6JUGdoAGGA== X-Received: by 2002:a7b:c94b:: with SMTP id i11mr1744214wml.113.1584711313846; Fri, 20 Mar 2020 06:35:13 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id f15sm8409789wru.83.2020.03.20.06.35.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 06:35:13 -0700 (PDT) From: Thierry Reding To: Thomas Gleixner , Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] arm64: tegra: Add native timer support on Tegra194 Date: Fri, 20 Mar 2020 14:34:51 +0100 Message-Id: <20200320133452.3705040-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200320133452.3705040-1-thierry.reding@gmail.com> References: <20200320133452.3705040-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra194. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 019f66f03a97..a0a5b44ff9bb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -213,6 +213,23 @@ emc: external-memory-controller@2c60000 { }; }; + timer@3010000 { + compatible = "nvidia,tegra194-timer", + "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; From patchwork Fri Mar 20 13:34:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1258910 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=eg61IfGR; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48kPsy17pdz9sSt for ; Sat, 21 Mar 2020 00:35:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727551AbgCTNf0 (ORCPT ); Fri, 20 Mar 2020 09:35:26 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:40410 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727511AbgCTNfS (ORCPT ); Fri, 20 Mar 2020 09:35:18 -0400 Received: by mail-wm1-f67.google.com with SMTP id a81so596049wmf.5; Fri, 20 Mar 2020 06:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fhOtbK0ZVL1ABebYKJYf0UxxzluO0JY5MJfCTLBiR34=; b=eg61IfGRG4RM8ATBwaJ4ZflHXV9nWhy7dN7OcN/Yia3AMeGSxeqQE8Ur1H1QiQSptW NzD7kEzRRXWhsycMK5RUD9ok0rOe7fTyZFhemfq1mYc4+00cpHoLEGkZ05f5zBchT1lm bRE+lS9yG87M4n6QpGK/aVcIfldB0NXrLEYyuNS1xW4Ie8v70Yh4v8BQwcTMZi8pKFla bDddRe0XGUNzhI9bFTpXPzpYnnqV5Hak0lM383qta3X10KbU8wCsPX5nQ5U54nVIKM5y pNUXz5Ex3pS4d5eWwxuZqyJX+E3JAwlFnzd8yidtsGVuvsmMwF1m8DDtCMa/qaNMgO7M Dwfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fhOtbK0ZVL1ABebYKJYf0UxxzluO0JY5MJfCTLBiR34=; b=Jg3rnTZ2gQ3tc+nvd1Ss+8o7Nply/b1fJG9RKzYJQ3Ufn0Nia28xx7/bG2bybfC4QI rLPuLjxQo1D5/IUuJu8d7yabRl6zyf8UFbbmkjDPcTjQcXVbj1cbwVUrlEAanwgFEeFa uKZ72cCfpJDDLLoXFETcOeex76IHxS9RhXmFWG2jS+rTcA9hIgBH/8Zu8odLPZlHYeMB 4SitFA2MW7yIsVga+7JZYN1RIYAAQx9NpOj+zfEM8Xx/rS2FiUshu6eL5BI0MIVTOoKr kAHzL+1pxoJ/UwEwS34pO76sHB4tr8XScM21SxuClH52iWGC2SescQ7nXFUTLMZ1uPN4 h1JA== X-Gm-Message-State: ANhLgQ1nJIc0BLBi1OSKJl4Cih37OPWt8cMH+Oz1J30vGzq/bZi2JBo8 fXr5Af5Zxul8ENEFY0yYdqQ= X-Google-Smtp-Source: ADFU+vuLxcyO2KD5jaTVUfpSqHOfct7nsy9xBH35W2ZSyqKfS427VdekhuvEWxvY0ML9TdMPqddS6A== X-Received: by 2002:a1c:7f10:: with SMTP id a16mr10159562wmd.1.1584711316042; Fri, 20 Mar 2020 06:35:16 -0700 (PDT) Received: from localhost (pD9E51CDC.dip0.t-ipconnect.de. [217.229.28.220]) by smtp.gmail.com with ESMTPSA id v21sm3105535wmj.8.2020.03.20.06.35.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 06:35:14 -0700 (PDT) From: Thierry Reding To: Thomas Gleixner , Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: tegra: Enable native timers on Jetson AGX Xavier Date: Fri, 20 Mar 2020 14:34:52 +0100 Message-Id: <20200320133452.3705040-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200320133452.3705040-1-thierry.reding@gmail.com> References: <20200320133452.3705040-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Enable the native timers on Jetson AGX Xavier to allow using the watchdog functionality to recover from system hangs, for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 623f7d7d216b..d68588f2709e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -52,6 +52,10 @@ memory-controller@2c00000 { status = "okay"; }; + timer@3010000 { + status = "okay"; + }; + serial@3110000 { status = "okay"; };