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[U-Boot] powerpc/85xx: Fix NAND SPL support

Message ID 1320851736-19205-1-git-send-email-galak@kernel.crashing.org
State Accepted
Commit 8d22ddca3db2577b7f2bf1040972231279288847
Delegated to: Kumar Gala
Headers show

Commit Message

Kumar Gala Nov. 9, 2011, 3:15 p.m. UTC
We cause CCSRBAR to be relocated in the SPL phase of NAND boot which
isn't expected and breaks things.  Fixing the board config.h to NOT
relocate CCSR during the CONFIG_NAND_SPL phase.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/MPC8536DS.h    |    2 +-
 include/configs/MPC8569MDS.h   |    2 +-
 include/configs/MPC8572DS.h    |    2 +-
 include/configs/P1_P2_RDB.h    |    2 +-
 include/configs/p1_p2_rdb_pc.h |    2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

Comments

Kumar Gala Nov. 11, 2011, 1:33 p.m. UTC | #1
On Nov 9, 2011, at 9:15 AM, Kumar Gala wrote:

> We cause CCSRBAR to be relocated in the SPL phase of NAND boot which
> isn't expected and breaks things.  Fixing the board config.h to NOT
> relocate CCSR during the CONFIG_NAND_SPL phase.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> include/configs/MPC8536DS.h    |    2 +-
> include/configs/MPC8569MDS.h   |    2 +-
> include/configs/MPC8572DS.h    |    2 +-
> include/configs/P1_P2_RDB.h    |    2 +-
> include/configs/p1_p2_rdb_pc.h |    2 +-
> 5 files changed, 5 insertions(+), 5 deletions(-)

applied

- k
diff mbox

Patch

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index d4e3ef5..16db98f 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -131,7 +131,7 @@ 
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 19d3271..ab27b98 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -108,7 +108,7 @@  extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR		0xe0000000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index ffee8fc..d7910e1 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -115,7 +115,7 @@ 
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 883d44e..00fa74d 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -151,7 +151,7 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index bcfb034..5a69902 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -221,7 +221,7 @@ 
 
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
-#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif