diff mbox series

[3/4,ARC] Deprecate q-class option.

Message ID 20200203113832.20270-3-claziss@gmail.com
State New
Headers show
Series [1/4,ARC] Update mlo/mhi handling when big-endian CPU. | expand

Commit Message

Claudiu Zissulescu Ianculescu Feb. 3, 2020, 11:38 a.m. UTC 
This option was used to control the short instruction selection.  However,
there is no difference in cycles if we use or not a short instruction,
and always someone wants a smaller program.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
	R12-R15 are always in ARCOMPACT16_REGS register class.
	* config/arc/arc.opt (mq-class): Deprecate.
	* config/arc/constraint.md ("q"): Remove dependency on mq-class
	option.
	* doc/invoke.texi (mq-class): Update text.
	* common/config/arc/arc-common.c (arc_option_optimization_table):
	Update list.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/nps400-1.c: Update test.
---
 gcc/common/config/arc/arc-common.c      | 1 -
 gcc/config/arc/arc.c                    | 3 +--
 gcc/config/arc/arc.opt                  | 2 +-
 gcc/config/arc/constraints.md           | 2 +-
 gcc/doc/invoke.texi                     | 2 +-
 gcc/testsuite/gcc.target/arc/nps400-1.c | 2 +-
 6 files changed, 5 insertions(+), 7 deletions(-)

Comments

Jeff Law Feb. 3, 2020, 4:25 p.m. UTC | #1 
On Mon, 2020-02-03 at 12:38 +0100, Claudiu Zissulescu wrote:
> This option was used to control the short instruction selection.  However,
> there is no difference in cycles if we use or not a short instruction,
> and always someone wants a smaller program.
> 
> gcc/
> xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
> 	R12-R15 are always in ARCOMPACT16_REGS register class.
> 	* config/arc/arc.opt (mq-class): Deprecate.
> 	* config/arc/constraint.md ("q"): Remove dependency on mq-class
> 	option.
> 	* doc/invoke.texi (mq-class): Update text.
> 	* common/config/arc/arc-common.c (arc_option_optimization_table):
> 	Update list.
OK.
jeff
>
diff mbox series

Patch

diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c
index 0f73cc4dd18..0b77dd546e5 100644
--- a/gcc/common/config/arc/arc-common.c
+++ b/gcc/common/config/arc/arc-common.c
@@ -56,7 +56,6 @@  static const struct default_options arc_option_optimization_table[] =
     { OPT_LEVELS_SIZE, OPT_fbranch_count_reg, NULL, 0},
     { OPT_LEVELS_SIZE, OPT_fdelayed_branch, NULL, 0 },
     { OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
-    { OPT_LEVELS_SIZE, OPT_mq_class, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
     { OPT_LEVELS_SIZE, OPT_mmillicode, NULL, 1 },
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index bd1e12b8a1f..960645fdfbf 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1965,8 +1965,7 @@  arc_conditional_register_usage (void)
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     if (i < ILINK1_REG)
       {
-	if ((TARGET_Q_CLASS || TARGET_RRQ_CLASS)
-	    && ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG))))
+	if ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG)))
 	  arc_regno_reg_class[i] = ARCOMPACT16_REGS;
 	else
 	  arc_regno_reg_class[i] = GENERAL_REGS;
diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 72d72570629..45c2f5c36ad 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -316,7 +316,7 @@  Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 Use pc-relative switch case tables - this enables case table shortening.
 
 mq-class
-Target Var(TARGET_Q_CLASS)
+Target Warn(%qs is deprecated)
 Enable 'q' instruction alternatives.
 
 mxy
diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md
index 3be2a8abab0..b7a563a72ad 100644
--- a/gcc/config/arc/constraints.md
+++ b/gcc/config/arc/constraints.md
@@ -53,7 +53,7 @@ 
 (define_register_constraint "x" "R0_REGS"
   "@code{R0} register.")
 
-(define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS"
+(define_register_constraint "q" "ARCOMPACT16_REGS"
   "Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
    @code{r12}-@code{r15}")
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 90eab1e7a6d..178832c0729 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17795,7 +17795,7 @@  code-density feature.
 
 @item -mq-class
 @opindex mq-class
-Enable @samp{q} instruction alternatives.
+Ths option is deprecated.  Enable @samp{q} instruction alternatives.
 This is the default for @option{-Os}.
 
 @item -mRcq
diff --git a/gcc/testsuite/gcc.target/arc/nps400-1.c b/gcc/testsuite/gcc.target/arc/nps400-1.c
index 504aad734cc..29486a30ee9 100644
--- a/gcc/testsuite/gcc.target/arc/nps400-1.c
+++ b/gcc/testsuite/gcc.target/arc/nps400-1.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile } */
 /* { dg-skip-if "" { ! { clmcpu } } } */
-/* { dg-options "-mcpu=nps400 -mq-class -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */
+/* { dg-options "-mcpu=nps400 -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */
 
 enum npsdp_mem_space_type {
   NPSDP_EXTERNAL_MS = 1