From patchwork Mon Feb 3 11:38:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 1232724 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-518746-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=P8AFYAu4; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=KGlIsoq3; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48B5SW0dW0z9sPK for ; Mon, 3 Feb 2020 22:38:50 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; q=dns; s=default; b=UUeUV334+0lKQV4T 9Y5dXGqUbqaSwJcRo7f9hyegRhpjmsYUj/gkotv4Stzvr4w4XanzrvM/1KIL8tIU a5CD9XaeTzcopQ0V4xpSLUDYnPip961YOFL28Ol7SLUGlpkNkJU/8pVjpp5CaSwz tpX0y7bWZW3RNapITI1qFE3+DwA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=default; bh=Xvcg7jYup9nitrRadmcQW8 qSW8M=; b=P8AFYAu4YI+Neqms4z7klgpgZgmxvR2l4WTtjcQMmxOLf+y85qzGih o2IL1bQFrimdoiZ+JCk6YG5ssO5Sa9QNaeTX6XsEoiHlCyd7fJLN92ALQtOhCZoI sXu0GykIFd4hwpuFjlZetW1XyrcNGOG75ciCiQKg3lGvL3SzxcR1c= Received: (qmail 59228 invoked by alias); 3 Feb 2020 11:38:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59220 invoked by uid 89); 3 Feb 2020 11:38:43 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=mbig-endian, mbigendian, emit_move_insn, rr X-HELO: mail-wm1-f68.google.com Received: from mail-wm1-f68.google.com (HELO mail-wm1-f68.google.com) (209.85.128.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Feb 2020 11:38:41 +0000 Received: by mail-wm1-f68.google.com with SMTP id s10so15469692wmh.3 for ; Mon, 03 Feb 2020 03:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DyU2jiGK3muEAOjqGyp7wBBV9bDmrUlN3/2onUUy0ew=; b=KGlIsoq3coeYV4jwGWIG7av0Ucw0cOkJz1dkLPLNWOWojot/z1/H1Bj45FekypDpVY DzmhBSs2bxnldH2D37zTin8D0jDAmaJPQQA+IMbWQiDI/9uiINhKETaDJJqL4mUbA6ym QdFe5DWdjppxN1bV/7hnJD6tmNo628H1GREnB7zzPwXn8mVpJnI34GYAuoI/PbAt2NDV UXGsKxdACnQZmNKskW/LwXcF1iIorRCl+3pMuQC7Z8K0c4c5VBFcEjYBO1ZJ9rZJvweU WbR01DlNRYrfX1osDWkQqe2EFD7KDnOhwizGFaETpBbIfL5vk24Zygd1iu/2+8r93nio GVpA== Received: from engy.ddns.hightechcampus.nl ([80.255.245.234]) by smtp.gmail.com with ESMTPSA id 5sm22030481wrc.75.2020.02.03.03.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 03:38:38 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, law@redhat.com Subject: [PATCH 1/4] [ARC] Update mlo/mhi handling when big-endian CPU. Date: Mon, 3 Feb 2020 12:38:29 +0100 Message-Id: <20200203113832.20270-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes The ARC 600 MUL64 instructions are using mlo/mhi registers to pass the 64-bit result. However, the mlo/mhi registers are not swapping depending on endianess. Update multiplication patterns to reflect this fact. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi registers. (umulsidi_600): Likewise. testsuite/ xxxx-xx-xx Claudiu Zissulescu Petro Karashchenko * estsuite/gcc.target/arc/mul64-1.c: New test. --- gcc/config/arc/arc.md | 50 ++++++++++++++++---------- gcc/testsuite/gcc.target/arc/mul64-1.c | 23 ++++++++++++ 2 files changed, 55 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/mul64-1.c diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 9a96440025f..f19f2c32641 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2288,19 +2288,26 @@ archs4x, archs4xd" (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) (define_insn_and_split "mulsidi_600" - [(set (match_operand:DI 0 "register_operand" "=c, c,c, c") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%Rcq#q, c,c, c")) - (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "Rcq#q,cL,L,C32")))) - (clobber (reg:DI MUL64_OUT_REG))] + [(set (match_operand:DI 0 "register_operand" "=r,r, r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r,r, r")) + (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "rL,L,C32")))) + (clobber (reg:DI R58_REG))] "TARGET_MUL64_SET" "#" - "TARGET_MUL64_SET" + "TARGET_MUL64_SET && reload_completed" [(const_int 0)] - "emit_insn (gen_mul64 (operands[1], operands[2])); - emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); - DONE;" + { + int hi = !TARGET_BIG_ENDIAN; + int lo = !hi; + rtx lr = operand_subword (operands[0], lo, 0, DImode); + rtx hr = operand_subword (operands[0], hi, 0, DImode); + emit_insn (gen_mul64 (operands[1], operands[2])); + emit_move_insn (lr, gen_rtx_REG (SImode, R58_REG)); + emit_move_insn (hr, gen_rtx_REG (SImode, R59_REG)); + DONE; + } [(set_attr "type" "multi") - (set_attr "length" "8")]) + (set_attr "length" "4,4,8")]) (define_insn "mul64" [(set (reg:DI MUL64_OUT_REG) @@ -2316,19 +2323,26 @@ archs4x, archs4xd" (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) (define_insn_and_split "umulsidi_600" - [(set (match_operand:DI 0 "register_operand" "=c,c, c") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c,c, c")) - (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "cL,L,C32")))) - (clobber (reg:DI MUL64_OUT_REG))] + [(set (match_operand:DI 0 "register_operand" "=r,r, r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r,r, r")) + (zero_extend:DI (match_operand:SI 2 "nonmemory_operand" "rL,L,C32")))) + (clobber (reg:DI R58_REG))] "TARGET_MUL64_SET" "#" - "TARGET_MUL64_SET" + "TARGET_MUL64_SET && reload_completed" [(const_int 0)] - "emit_insn (gen_mulu64 (operands[1], operands[2])); - emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); - DONE;" + { + int hi = !TARGET_BIG_ENDIAN; + int lo = !hi; + rtx lr = operand_subword (operands[0], lo, 0, DImode); + rtx hr = operand_subword (operands[0], hi, 0, DImode); + emit_insn (gen_mulu64 (operands[1], operands[2])); + emit_move_insn (lr, gen_rtx_REG (SImode, R58_REG)); + emit_move_insn (hr, gen_rtx_REG (SImode, R59_REG)); + DONE; + } [(set_attr "type" "umulti") - (set_attr "length" "8")]) + (set_attr "length" "4,4,8")]) (define_insn "mulu64" [(set (reg:DI MUL64_OUT_REG) diff --git a/gcc/testsuite/gcc.target/arc/mul64-1.c b/gcc/testsuite/gcc.target/arc/mul64-1.c new file mode 100644 index 00000000000..2543fc33d3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/mul64-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-skip-if "MUL64 is ARC600 extension." { ! { clmcpu } } } */ +/* { dg-options "-O2 -mmul64 -mbig-endian -mcpu=arc600" } */ + +/* Check if mlo/mhi registers are correctly layout when we compile for + a big-endian CPU. */ + +#include + +uint32_t foo (uint32_t x) +{ + return x % 1000; +} + +int32_t bar (int32_t x) +{ + return x % 1000; +} + +/* { dg-final { scan-assembler-times "\\s+mul64\\s+" 3 } } */ +/* { dg-final { scan-assembler-times "\\s+mulu64\\s+" 1 } } */ +/* { dg-final { scan-assembler-times "r\[0-9\]+,mhi" 2 } } */ +/* { dg-final { scan-assembler-times "r\[0-9\]+,mlo" 2 } } */ From patchwork Mon Feb 3 11:38:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 1232726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-518748-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=Mp003rYl; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Y0DiJVQb; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48B5Sz5rySz9sPK for ; Mon, 3 Feb 2020 22:39:15 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=Ydy /+6OuF+X9gbKhJdn9pdX8TeynXThQQ2tXLRTCaEJK53k7jtxv6o2a4TrPt49u5SD TKxW35HvyrAWTz1UqHvsV8nhdgz63aMiox6jvCiP2+Us0neANDKn9paH9N5z/JFu B5GY1SaV3s5MVe3UsmsWT27EAXkX2LhmsFEjY+Qg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=4pvhjuRIN r/C3e2T4IHpMT4C5L4=; b=Mp003rYly9/8Zf7WpdZbxpoeWr3AbTeA4OgabsiDQ suO/7CUBpBRQMTc6az4vB3INJH+ji6Cg3KEMT7DaIDeFfhMHQCHI2tYmQg11mYzj 89N1aXMKgdXB0PV4BPyfg0Wv1N/3H/sf+jclJnQkhjw3ZtOpllOQD9zO7uTRiJ3A Wg= Received: (qmail 59488 invoked by alias); 3 Feb 2020 11:38:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59302 invoked by uid 89); 3 Feb 2020 11:38:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.7 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=additive, Due, qq, classical X-HELO: mail-wr1-f67.google.com Received: from mail-wr1-f67.google.com (HELO mail-wr1-f67.google.com) (209.85.221.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Feb 2020 11:38:42 +0000 Received: by mail-wr1-f67.google.com with SMTP id t2so17624726wrr.1 for ; Mon, 03 Feb 2020 03:38:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u0G4Fn6vydHpfCGtRonb3zVszssN0VcwthRGEB9OYg4=; b=Y0DiJVQbVBYtbeLDf/kq5h1CokMJhZ1Tt4bRugctrtd/aXqHvwaxMIyt+WpA0TJyBu IOzjqgRflThSPIS+44jv46OxDEkuAuhWFz7mI/MphHHy4qfpVHASLkCL9Sgf+4qFLdJE KQKRwJKZ5jbqa+vr9a3Yg2ztNse82woqlsjSKxWV2G+Ax9f8LTe7ncp3q7FMDrRVrch9 SWwmg5yQhzi1fgX7EaZ6vg1r01LMSFxDUvwSmgyTBIV2dDj4mr2RTLY4jIKuj7OtaZkg l5YqEzXcFv0bps9qUaUa/Asx4ZNHQ2GFv+Kd3EAStEL/iW5SIwa7zFHLz8P3Lc6YmJY9 DbKA== Received: from engy.ddns.hightechcampus.nl ([80.255.245.234]) by smtp.gmail.com with ESMTPSA id 5sm22030481wrc.75.2020.02.03.03.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 03:38:39 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, law@redhat.com Subject: [PATCH 2/4] [ARC] Use TARGET_INSN_COST. Date: Mon, 3 Feb 2020 12:38:30 +0100 Message-Id: <20200203113832.20270-2-claziss@gmail.com> In-Reply-To: <20200203113832.20270-1-claziss@gmail.com> References: <20200203113832.20270-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes TARGET_INSN_COST gives us a better control over the instruction costs than classical RTX_COSTS. A simple cost scheme is in place for the time being, when optimizing for size, the cost is given by the instruction length. When optimizing for speed, the cost is 1 for any recognized instruction, and 2 for any load/store instruction. The latter one can be overwritten by using cost attribute for an instruction. Due to this change, we need to update also a number of instruction patterns with a new predicate to better reflect the costs. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.c (arc_insn_cost): New function. (TARGET_INSN_COST): Define. * config/arc/arc.md (cost): New attribute. (add_n): Use arc_nonmemory_operand. (ashlsi3_insn): Likewise, also update constraints. (ashrsi3_insn): Likewise. (rotrsi3): Likewise. (add_shift): Likewise. * config/arc/predicates.md (arc_nonmemory_operand): New predicate. testsuite/ xxxx-xx-xx Claudiu Zissulescu * gcc.target/arc/or-cnst-size2.c: Update test. --- gcc/config/arc/arc.c | 52 ++++++++++++++++++++ gcc/config/arc/arc.md | 47 +++++++++--------- gcc/config/arc/predicates.md | 5 ++ gcc/testsuite/gcc.target/arc/or-cnst-size2.c | 2 +- 4 files changed, 83 insertions(+), 23 deletions(-) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 7fa0fb51a4b..bd1e12b8a1f 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -11786,6 +11786,55 @@ arc_can_use_return_insn (void) && !ARC_INTERRUPT_P (arc_compute_function_type (cfun))); } +/* Helper for INSN_COST. + + Per Segher Boessenkool: rtx_costs computes the cost for any rtx (an + insn, a set, a set source, any random piece of one). set_src_cost, + set_rtx_cost, etc. are helper functions that use that. + + Those functions do not work for parallels. Also, costs are not + additive like this simplified model assumes. Also, more complex + backends tend to miss many cases in their rtx_costs function. + + Many passes that want costs want to know the cost of a full insn. Like + combine. That's why I created insn_cost: it solves all of the above + problems. */ + +static int +arc_insn_cost (rtx_insn *insn, bool speed) +{ + int cost; + if (recog_memoized (insn) < 0) + return 0; + + /* If optimizing for size, we want the insn size. */ + if (!speed) + return get_attr_length (insn); + + /* Use cost if provided. */ + cost = get_attr_cost (insn); + if (cost > 0) + return cost; + + /* For speed make a simple cost model: memory access is more + expensive than any other instruction. */ + enum attr_type type = get_attr_type (insn); + + switch (type) + { + case TYPE_LOAD: + case TYPE_STORE: + cost = COSTS_N_INSNS (2); + break; + + default: + cost = COSTS_N_INSNS (1); + break; + } + + return cost; +} + #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p @@ -11807,6 +11856,9 @@ arc_can_use_return_insn (void) #undef TARGET_MEMORY_MOVE_COST #define TARGET_MEMORY_MOVE_COST arc_memory_move_cost +#undef TARGET_INSN_COST +#define TARGET_INSN_COST arc_insn_cost + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-arc.h" diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index f19f2c32641..fb25aafb024 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -229,6 +229,10 @@ ] ) +;; What is the insn_cost for this insn? The target hook can still override +;; this. For optimizing for size the "length" attribute is used instead. +(define_attr "cost" "" (const_int 0)) + (define_attr "is_sfunc" "no,yes" (const_string "no")) ;; Insn type. Used to default other attribute values. @@ -3140,9 +3144,9 @@ archs4x, archs4xd" [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r") (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "q,r,r") (match_operand:SI 2 "_2_4_8_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))] + (match_operand:SI 3 "arc_nonmemory_operand" "0,r,Csz")))] "" - "add%z2%?\\t%0,%3,%1%&" + "add%z2%?\\t%0,%3,%1" [(set_attr "type" "shift") (set_attr "length" "*,4,8") (set_attr "predicable" "yes,no,no") @@ -3573,26 +3577,26 @@ archs4x, archs4xd" ; to truncate a symbol in a u6 immediate; but that's rather exotic, so only ; provide one alternatice for this, without condexec support. (define_insn "*ashlsi3_insn" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") - (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz") - (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, q, r, r, r") + (ashift:SI (match_operand:SI 1 "arc_nonmemory_operand" "!0,q, 0, 0, r,rCsz") + (match_operand:SI 2 "nonmemory_operand" "K,K,qM,rL,rL,rCal")))] "TARGET_BARREL_SHIFTER && (register_operand (operands[1], SImode) || register_operand (operands[2], SImode))" - "asl%? %0,%1,%2%&" + "asl%?\\t%0,%1,%2" [(set_attr "type" "shift") (set_attr "iscompact" "maybe,maybe,maybe,false,false,false") (set_attr "predicable" "no,no,no,yes,no,no") (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")]) (define_insn "*ashrsi3_insn" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") - (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz") - (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, q, r, r, r") + (ashiftrt:SI (match_operand:SI 1 "arc_nonmemory_operand" "!0,q, 0, 0, r,rCsz") + (match_operand:SI 2 "nonmemory_operand" "K,K,qM,rL,rL,rCal")))] "TARGET_BARREL_SHIFTER && (register_operand (operands[1], SImode) || register_operand (operands[2], SImode))" - "asr%? %0,%1,%2%&" + "asr%?\\t%0,%1,%2" [(set_attr "type" "shift") (set_attr "iscompact" "maybe,maybe,maybe,false,false,false") (set_attr "predicable" "no,no,no,yes,no,no") @@ -3613,11 +3617,11 @@ archs4x, archs4xd" (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")]) (define_insn "rotrsi3" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w") - (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCsz") - (match_operand:SI 2 "nonmemory_operand" "cL,cL,cCal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=r, r, r") + (rotatert:SI (match_operand:SI 1 "arc_nonmemory_operand" " 0,rL,rCsz") + (match_operand:SI 2 "nonmemory_operand" "rL,rL,rCal")))] "TARGET_BARREL_SHIFTER" - "ror%? %0,%1,%2" + "ror%?\\t%0,%1,%2" [(set_attr "type" "shift,shift,shift") (set_attr "predicable" "yes,no,no") (set_attr "length" "4,4,8")]) @@ -4349,16 +4353,15 @@ archs4x, archs4xd" (ashift:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "_1_2_3_operand" ""))) (set (match_operand:SI 3 "dest_reg_operand" "") - (plus:SI (match_operand:SI 4 "nonmemory_operand" "") - (match_operand:SI 5 "nonmemory_operand" "")))] + (plus:SI (match_operand:SI 4 "arc_nonmemory_operand" "") + (match_operand:SI 5 "arc_nonmemory_operand" "")))] "(true_regnum (operands[4]) == true_regnum (operands[0]) || true_regnum (operands[5]) == true_regnum (operands[0])) && (peep2_reg_dead_p (2, operands[0]) - || (true_regnum (operands[3]) == true_regnum (operands[0]))) - && !(optimize_size && satisfies_constraint_I (operands[4])) - && !(optimize_size && satisfies_constraint_I (operands[5]))" - ;; the preparation statements take care to put proper operand in operands[4] - ;; operands[4] will always contain the correct operand. This is added to satisfy commutativity + || (true_regnum (operands[3]) == true_regnum (operands[0])))" + ;; the preparation statements take care to put proper operand in + ;; operands[4] operands[4] will always contain the correct + ;; operand. This is added to satisfy commutativity [(set (match_dup 3) (plus:SI (mult:SI (match_dup 1) (match_dup 2)) @@ -6435,7 +6438,7 @@ archs4x, archs4xd" [(set (match_operand:SI 0 "register_operand" "=q,r,r") (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "q,r,r") (match_operand:SI 2 "_1_2_3_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))] + (match_operand:SI 3 "arc_nonmemory_operand" "0,r,Csz")))] "" "add%2%?\\t%0,%3,%1" [(set_attr "length" "*,4,8") diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index 3c03436c901..2ad476d5755 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -795,3 +795,8 @@ { return arc_check_multi (op, false); }) + +(define_predicate "arc_nonmemory_operand" + (ior (match_test "register_operand (op, mode)") + (and (match_code "const_int, symbol_ref") + (match_test "!optimize_size")))) diff --git a/gcc/testsuite/gcc.target/arc/or-cnst-size2.c b/gcc/testsuite/gcc.target/arc/or-cnst-size2.c index 33af97bbdbf..8fa1e65c7f6 100644 --- a/gcc/testsuite/gcc.target/arc/or-cnst-size2.c +++ b/gcc/testsuite/gcc.target/arc/or-cnst-size2.c @@ -9,4 +9,4 @@ int foo (void) } /* { dg-final { scan-assembler "tst" } } */ -/* { dg-final { scan-assembler "bset.eq" } } */ +/* { dg-final { scan-assembler "bset" } } */ From patchwork Mon Feb 3 11:38:31 2020 Content-Type: text/plain; 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Date: Mon, 3 Feb 2020 12:38:31 +0100 Message-Id: <20200203113832.20270-3-claziss@gmail.com> In-Reply-To: <20200203113832.20270-1-claziss@gmail.com> References: <20200203113832.20270-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes This option was used to control the short instruction selection. However, there is no difference in cycles if we use or not a short instruction, and always someone wants a smaller program. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and R12-R15 are always in ARCOMPACT16_REGS register class. * config/arc/arc.opt (mq-class): Deprecate. * config/arc/constraint.md ("q"): Remove dependency on mq-class option. * doc/invoke.texi (mq-class): Update text. * common/config/arc/arc-common.c (arc_option_optimization_table): Update list. testsuite/ xxxx-xx-xx Claudiu Zissulescu * gcc.target/arc/nps400-1.c: Update test. --- gcc/common/config/arc/arc-common.c | 1 - gcc/config/arc/arc.c | 3 +-- gcc/config/arc/arc.opt | 2 +- gcc/config/arc/constraints.md | 2 +- gcc/doc/invoke.texi | 2 +- gcc/testsuite/gcc.target/arc/nps400-1.c | 2 +- 6 files changed, 5 insertions(+), 7 deletions(-) diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index 0f73cc4dd18..0b77dd546e5 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -56,7 +56,6 @@ static const struct default_options arc_option_optimization_table[] = { OPT_LEVELS_SIZE, OPT_fbranch_count_reg, NULL, 0}, { OPT_LEVELS_SIZE, OPT_fdelayed_branch, NULL, 0 }, { OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 }, - { OPT_LEVELS_SIZE, OPT_mq_class, NULL, 1 }, { OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 }, { OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 }, { OPT_LEVELS_SIZE, OPT_mmillicode, NULL, 1 }, diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index bd1e12b8a1f..960645fdfbf 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1965,8 +1965,7 @@ arc_conditional_register_usage (void) for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) if (i < ILINK1_REG) { - if ((TARGET_Q_CLASS || TARGET_RRQ_CLASS) - && ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG)))) + if ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG))) arc_regno_reg_class[i] = ARCOMPACT16_REGS; else arc_regno_reg_class[i] = GENERAL_REGS; diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 72d72570629..45c2f5c36ad 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -316,7 +316,7 @@ Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) Use pc-relative switch case tables - this enables case table shortening. mq-class -Target Var(TARGET_Q_CLASS) +Target Warn(%qs is deprecated) Enable 'q' instruction alternatives. mxy diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 3be2a8abab0..b7a563a72ad 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -53,7 +53,7 @@ (define_register_constraint "x" "R0_REGS" "@code{R0} register.") -(define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS" +(define_register_constraint "q" "ARCOMPACT16_REGS" "Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 90eab1e7a6d..178832c0729 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17795,7 +17795,7 @@ code-density feature. @item -mq-class @opindex mq-class -Enable @samp{q} instruction alternatives. +Ths option is deprecated. Enable @samp{q} instruction alternatives. This is the default for @option{-Os}. @item -mRcq diff --git a/gcc/testsuite/gcc.target/arc/nps400-1.c b/gcc/testsuite/gcc.target/arc/nps400-1.c index 504aad734cc..29486a30ee9 100644 --- a/gcc/testsuite/gcc.target/arc/nps400-1.c +++ b/gcc/testsuite/gcc.target/arc/nps400-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-skip-if "" { ! { clmcpu } } } */ -/* { dg-options "-mcpu=nps400 -mq-class -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */ +/* { dg-options "-mcpu=nps400 -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */ enum npsdp_mem_space_type { NPSDP_EXTERNAL_MS = 1 From patchwork Mon Feb 3 11:38:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 1232727 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-518749-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=a776HVVu; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=oULeQzzy; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48B5TC3s98z9sPK for ; Mon, 3 Feb 2020 22:39:27 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=xJS HkdiLhKwF71ztpx2rPQYy0D98LTSZrcQaVA6lf+B3sAN0zRqMjw0izRZaa3n3bgW 8MEL8hdX5YAofD9kuFlHP8MC+LMhdTD9ztE/wNWvQYJZhRk7xo8OqmzN0pmuQ8tz k68/jkwiHyRSBadDh7Tv55wGqcTuMY7bKbmY1aU4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=XD8Md3rIt NTJzsri2p19ohv9j5o=; b=a776HVVuY3dE3HRxj2ktgMtIxxVpgyEMC1rl6k0Nm P4GUk9RmS315HBPj5h31UTSy1TApljhZxJtoT2gX4b595mWsYvsq5DCA3NIq0y2b Vp3vE/NxZ8HHgAAZJEyZxd1TisEV1f5Mm2+IQRse33jQzQMzIqZXUMJ3RceJijBl OA= Received: (qmail 59544 invoked by alias); 3 Feb 2020 11:38:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59412 invoked by uid 89); 3 Feb 2020 11:38:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.4 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-wr1-f48.google.com Received: from mail-wr1-f48.google.com (HELO mail-wr1-f48.google.com) (209.85.221.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Feb 2020 11:38:44 +0000 Received: by mail-wr1-f48.google.com with SMTP id u6so4311326wrt.0 for ; Mon, 03 Feb 2020 03:38:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Evu+amidQbGT8LaJiTAyBjdebwCb6/BbpyaG0eyfpE=; b=oULeQzzyyf9w3DngnmGQlF/2+zEDfH0W6rlCytZQMQuWCnIZbM4GSTmnnCY6PVBuWh PauVIrB/eF/B0aLq3vGYw7XP9la7jR1CpPj6z9jXeEiWWvDa5JXfhtcB4XPAWwS2INVD vAOu0v2s0c6NducJbrCx17S12Q0cE7iQNJy952F0ynShUb4K4kEv6+So+Yd92a23FjYF 7LLX1kT1eHI9gKUrtJht4uWiLelveYepMUVUtMrakK5tiM8mObB4g059VerjDJCA5z6e QXaE+ac+KyrLXNokK8pq0Yf0tH2L5PDwtBRjlNUGGW+sy9lxayRIL9NNC3X9g83WjaEg BMfQ== Received: from engy.ddns.hightechcampus.nl ([80.255.245.234]) by smtp.gmail.com with ESMTPSA id 5sm22030481wrc.75.2020.02.03.03.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 03:38:41 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, law@redhat.com Subject: [PATCH 4/4] arc: Don't use if-conversion when optimizing for size. Date: Mon, 3 Feb 2020 12:38:32 +0100 Message-Id: <20200203113832.20270-4-claziss@gmail.com> In-Reply-To: <20200203113832.20270-1-claziss@gmail.com> References: <20200203113832.20270-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes For ARC, predicated instructions are not very friendly with size optimizations, leading to increased object size. Disable if-conversion step when optimized for size. gcc/ xxxx-xx-xx Claudiu Zissulescu * common/config/arc/arc-common.c (arc_option_optimization_table): Disable if-conversion step when optimized for size. --- gcc/common/config/arc/arc-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c index 0b77dd546e5..7f46f547e30 100644 --- a/gcc/common/config/arc/arc-common.c +++ b/gcc/common/config/arc/arc-common.c @@ -59,6 +59,7 @@ static const struct default_options arc_option_optimization_table[] = { OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 }, { OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 }, { OPT_LEVELS_SIZE, OPT_mmillicode, NULL, 1 }, + { OPT_LEVELS_SIZE, OPT_fif_conversion, NULL, 0 }, { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 }, { OPT_LEVELS_NONE, 0, NULL, 0 }