| Message ID | 20200106042957.26494-2-yingjie_bai@126.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | eeb09917c138ccd6d9a1c8410891ca2fa5feb5ea |
| Delegated to: | Scott Wood |
| Headers | show |
| Series | [v3,1/2] powerpc32/booke: consistently return phys_addr_t in __pa() | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (9b930eacc2f2331e6ed17e5216075faa3e3dc408) |
| snowpatch_ozlabs/build-ppc64le | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64be | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64e | success | Build succeeded |
| snowpatch_ozlabs/build-pmac32 | success | Build succeeded |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 15 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch has no Fixes tags |
On Mon, 2020-01-06 at 12:29 +0800, yingjie_bai@126.com wrote: > From: Bai Yingjie <byj.tea@gmail.com> > > CPU like P4080 has 36bit physical address, its DDR physical > start address can be configured above 4G by LAW registers. > > For such systems in which their physical memory start address was > configured higher than 4G, we need also to write addr_h into the spin > table of the target secondary CPU, so that addr_h and addr_l together > represent a 64bit physical address. > Otherwise the secondary core can not get correct entry to start from. > > Signed-off-by: Bai Yingjie <byj.tea@gmail.com> > --- > arch/powerpc/platforms/85xx/smp.c | 9 +++++++++ > 1 file changed, 9 insertions(+) Acked-by: Scott Wood <oss@buserror.net> -Scott
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index 8c7ea2486bc0..48f7d96ae37d 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -252,6 +252,15 @@ static int smp_85xx_start_cpu(int cpu) out_be64((u64 *)(&spin_table->addr_h), __pa(ppc_function_entry(generic_secondary_smp_init))); #else +#ifdef CONFIG_PHYS_ADDR_T_64BIT + /* + * We need also to write addr_h to spin table for systems + * in which their physical memory start address was configured + * to above 4G, otherwise the secondary core can not get + * correct entry to start from. + */ + out_be32(&spin_table->addr_h, __pa(__early_start) >> 32); +#endif out_be32(&spin_table->addr_l, __pa(__early_start)); #endif flush_spin_table(spin_table);