| Message ID | 20191126211206.4537-2-linux.amoon@gmail.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Neil Armstrong |
| Headers | show |
| Series | Odroid n2 using eMMC would fail to boot up | expand |
Hi, On 26/11/2019 22:12, Anand Moon wrote: > odroid n2 eMMC module would failed to boot up, > because of TX phase clk failure, fix the typo in > TX phase macro to help tune correct clk freqency. > > Before these changes. > clock is enabled (380953Hz) > clock is enabled (25000000Hz) > after these changes > clock is enabled (380953Hz) > clock is enabled (25000000Hz) > clock is enabled (52000000Hz) > clock is enabled (52000000Hz) > clock is enabled (52000000Hz) > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > --- > Tested on > new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 > old back - eMMC CGND3R 58.2 GiB MMC 5.0 > --- > drivers/mmc/meson_gx_mmc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c > index 031cc79ccb..87bea2888b 100644 > --- a/drivers/mmc/meson_gx_mmc.c > +++ b/drivers/mmc/meson_gx_mmc.c > @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc) > meson_mmc_clk |= CLK_CO_PHASE_180; > > /* 180 phase tx clock */ > - meson_mmc_clk |= CLK_TX_PHASE_000; > + meson_mmc_clk |= CLK_TX_PHASE_180; > > /* clock settings */ > meson_mmc_clk |= clk_src; > I don't understand what this change helps, the linux driver sets the TX phase to 0, why 180 would help here ? Neil
Hi Neil, On Wed, 27 Nov 2019 at 18:30, Neil Armstrong <narmstrong@baylibre.com> wrote: > > Hi, > > On 26/11/2019 22:12, Anand Moon wrote: > > odroid n2 eMMC module would failed to boot up, > > because of TX phase clk failure, fix the typo in > > TX phase macro to help tune correct clk freqency. > > > > Before these changes. > > clock is enabled (380953Hz) > > clock is enabled (25000000Hz) > > after these changes > > clock is enabled (380953Hz) > > clock is enabled (25000000Hz) > > clock is enabled (52000000Hz) > > clock is enabled (52000000Hz) > > clock is enabled (52000000Hz) > > > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > > --- > > Tested on > > new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 > > old back - eMMC CGND3R 58.2 GiB MMC 5.0 > > --- > > drivers/mmc/meson_gx_mmc.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c > > index 031cc79ccb..87bea2888b 100644 > > --- a/drivers/mmc/meson_gx_mmc.c > > +++ b/drivers/mmc/meson_gx_mmc.c > > @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc) > > meson_mmc_clk |= CLK_CO_PHASE_180; > > > > /* 180 phase tx clock */ > > - meson_mmc_clk |= CLK_TX_PHASE_000; > > + meson_mmc_clk |= CLK_TX_PHASE_180; > > > > /* clock settings */ > > meson_mmc_clk |= clk_src; > > > > I don't understand what this change helps, the linux driver sets the TX phase to 0, > why 180 would help here ? > > Neil I narrow down to this small changes, without this small change it fails to detect the eMMC module. See the below log. U-Boot 2020.01-rc3-00082-g4b19b89ca4-dirty (Nov 27 2019 - 18:56:37 +0530) odroid-n2 Model: Hardkernel ODROID-N2 SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) DRAM: 3.8 GiB mmc_bind: alias ret=-2, devnum=-1 mmc_bind: alias ret=-2, devnum=-1 MMC: clock is enabled (380953Hz) clock is enabled (380953Hz) sd@ffe05000: 0, mmc@ffe07000: 1 In: serial@3000 Out: serial@3000 Err: serial@3000 Net: gpio_request_tail: Node 'ethernet@ff3f0000', property 'snps,reset-gpio', failed to request GPIO index 0: -2 Warning: ethernet@ff3f0000 (eth0) using random MAC address - 26:1e:2a:2a:67:d6 eth0: ethernet@ff3f0000 Hit any key to stop autoboot: 0 clock is disabled (0Hz) regulator_common_set_enable: dev='regulator-tflash_vdd', enable=1, delay=0, has_gpio=1 regulator_common_set_enable: done clock is enabled (380953Hz) Card did not respond to voltage select! gpio_request_tail: Node 'regulator-vcc_3v3', property 'gpio', failed to request GPIO index 0: -2 Regulator 'regulator-vcc_3v3' optional enable GPIO - not found! Error: -2 gpio_request_tail: Node 'regulator-flash_1v8', property 'gpio', failed to request GPIO index 0: -2 Regulator 'regulator-flash_1v8' optional enable GPIO - not found! Error: -2 clock is disabled (0Hz) regulator_common_set_enable: dev='regulator-vcc_3v3', enable=1, delay=0, has_gpio=0 clock is enabled (380953Hz) clock is enabled (25000000Hz) unable to select a mode switch to partitions #0, OK mmc1(part 0) is current device ** No partition table - mmc 1 ** MMC Device 2 not found no mmc device at slot 2 starting USB... Bus usb@ff500000: gpio_request_tail: Node 'regulator-vcc_5v', property 'gpio', failed to request GPIO index 0: -2 Regulator 'regulator-vcc_5v' optional enable GPIO - not found! Error: -2 regulator_common_set_enable: dev='regulator-usb_pwr_en', enable=1, delay=0, has_gpio=1 regulator_common_set_enable: done Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found -Anand
Hi, On 27/11/2019 15:42, Anand Moon wrote: > Hi Neil, > > On Wed, 27 Nov 2019 at 18:30, Neil Armstrong <narmstrong@baylibre.com> wrote: >> >> Hi, >> >> On 26/11/2019 22:12, Anand Moon wrote: >>> odroid n2 eMMC module would failed to boot up, >>> because of TX phase clk failure, fix the typo in >>> TX phase macro to help tune correct clk freqency. >>> >>> Before these changes. >>> clock is enabled (380953Hz) >>> clock is enabled (25000000Hz) >>> after these changes >>> clock is enabled (380953Hz) >>> clock is enabled (25000000Hz) >>> clock is enabled (52000000Hz) >>> clock is enabled (52000000Hz) >>> clock is enabled (52000000Hz) >>> >>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>> --- >>> Tested on >>> new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 >>> old back - eMMC CGND3R 58.2 GiB MMC 5.0 >>> --- >>> drivers/mmc/meson_gx_mmc.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c >>> index 031cc79ccb..87bea2888b 100644 >>> --- a/drivers/mmc/meson_gx_mmc.c >>> +++ b/drivers/mmc/meson_gx_mmc.c >>> @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc) >>> meson_mmc_clk |= CLK_CO_PHASE_180; >>> >>> /* 180 phase tx clock */ >>> - meson_mmc_clk |= CLK_TX_PHASE_000; >>> + meson_mmc_clk |= CLK_TX_PHASE_180; >>> >>> /* clock settings */ >>> meson_mmc_clk |= clk_src; >>> >> >> I don't understand what this change helps, the linux driver sets the TX phase to 0, >> why 180 would help here ? >> >> Neil > > I narrow down to this small changes, without this small change > it fails to detect the eMMC module. See the below log. > > U-Boot 2020.01-rc3-00082-g4b19b89ca4-dirty (Nov 27 2019 - 18:56:37 > +0530) odroid-n2 > > Model: Hardkernel ODROID-N2 > SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) > DRAM: 3.8 GiB > mmc_bind: alias ret=-2, devnum=-1 > mmc_bind: alias ret=-2, devnum=-1 > MMC: clock is enabled (380953Hz) > clock is enabled (380953Hz) > sd@ffe05000: 0, mmc@ffe07000: 1 > In: serial@3000 > Out: serial@3000 > Err: serial@3000 > Net: gpio_request_tail: Node 'ethernet@ff3f0000', property > 'snps,reset-gpio', failed to request GPIO index 0: -2 > > Warning: ethernet@ff3f0000 (eth0) using random MAC address - 26:1e:2a:2a:67:d6 > eth0: ethernet@ff3f0000 > Hit any key to stop autoboot: 0 > clock is disabled (0Hz) > regulator_common_set_enable: dev='regulator-tflash_vdd', enable=1, > delay=0, has_gpio=1 > regulator_common_set_enable: done > clock is enabled (380953Hz) > Card did not respond to voltage select! > gpio_request_tail: Node 'regulator-vcc_3v3', property 'gpio', failed > to request GPIO index 0: -2 > Regulator 'regulator-vcc_3v3' optional enable GPIO - not found! Error: -2 > gpio_request_tail: Node 'regulator-flash_1v8', property 'gpio', failed > to request GPIO index 0: -2 > Regulator 'regulator-flash_1v8' optional enable GPIO - not found! Error: -2 > clock is disabled (0Hz) > regulator_common_set_enable: dev='regulator-vcc_3v3', enable=1, > delay=0, has_gpio=0 > clock is enabled (380953Hz) > clock is enabled (25000000Hz) > unable to select a mode > switch to partitions #0, OK > mmc1(part 0) is current device > ** No partition table - mmc 1 ** > MMC Device 2 not found > no mmc device at slot 2 > starting USB... > Bus usb@ff500000: gpio_request_tail: Node 'regulator-vcc_5v', property > 'gpio', failed to request GPIO index 0: -2 > Regulator 'regulator-vcc_5v' optional enable GPIO - not found! Error: -2 > regulator_common_set_enable: dev='regulator-usb_pwr_en', enable=1, > delay=0, has_gpio=1 > regulator_common_set_enable: done > Register 3000140 NbrPorts 3 > Starting the controller > USB XHCI 1.10 > scanning bus usb@ff500000 for devices... 1 USB Device(s) found > scanning usb for storage devices... 0 Storage Device(s) found I have the same behavior with SEI610 on SM1, I need to check this fixes the issue... Neil > > -Anand >
Hi Anand, On 04/12/2019 10:26, Neil Armstrong wrote: > Hi, > > On 27/11/2019 15:42, Anand Moon wrote: >> Hi Neil, >> >> On Wed, 27 Nov 2019 at 18:30, Neil Armstrong <narmstrong@baylibre.com> wrote: >>> >>> Hi, >>> >>> On 26/11/2019 22:12, Anand Moon wrote: >>>> odroid n2 eMMC module would failed to boot up, >>>> because of TX phase clk failure, fix the typo in >>>> TX phase macro to help tune correct clk freqency. >>>> >>>> Before these changes. >>>> clock is enabled (380953Hz) >>>> clock is enabled (25000000Hz) >>>> after these changes >>>> clock is enabled (380953Hz) >>>> clock is enabled (25000000Hz) >>>> clock is enabled (52000000Hz) >>>> clock is enabled (52000000Hz) >>>> clock is enabled (52000000Hz) >>>> >>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com> >>>> --- >>>> Tested on >>>> new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 >>>> old back - eMMC CGND3R 58.2 GiB MMC 5.0 >>>> --- >>>> drivers/mmc/meson_gx_mmc.c | 2 +- >>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c >>>> index 031cc79ccb..87bea2888b 100644 >>>> --- a/drivers/mmc/meson_gx_mmc.c >>>> +++ b/drivers/mmc/meson_gx_mmc.c >>>> @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc) >>>> meson_mmc_clk |= CLK_CO_PHASE_180; >>>> >>>> /* 180 phase tx clock */ >>>> - meson_mmc_clk |= CLK_TX_PHASE_000; >>>> + meson_mmc_clk |= CLK_TX_PHASE_180; >>>> >>>> /* clock settings */ >>>> meson_mmc_clk |= clk_src; >>>> >>> >>> I don't understand what this change helps, the linux driver sets the TX phase to 0, >>> why 180 would help here ? >>> >>> Neil >> >> I narrow down to this small changes, without this small change >> it fails to detect the eMMC module. See the below log. >> >> U-Boot 2020.01-rc3-00082-g4b19b89ca4-dirty (Nov 27 2019 - 18:56:37 >> +0530) odroid-n2 >> >> Model: Hardkernel ODROID-N2 >> SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) >> DRAM: 3.8 GiB >> mmc_bind: alias ret=-2, devnum=-1 >> mmc_bind: alias ret=-2, devnum=-1 >> MMC: clock is enabled (380953Hz) >> clock is enabled (380953Hz) >> sd@ffe05000: 0, mmc@ffe07000: 1 >> In: serial@3000 >> Out: serial@3000 >> Err: serial@3000 >> Net: gpio_request_tail: Node 'ethernet@ff3f0000', property >> 'snps,reset-gpio', failed to request GPIO index 0: -2 >> >> Warning: ethernet@ff3f0000 (eth0) using random MAC address - 26:1e:2a:2a:67:d6 >> eth0: ethernet@ff3f0000 >> Hit any key to stop autoboot: 0 >> clock is disabled (0Hz) >> regulator_common_set_enable: dev='regulator-tflash_vdd', enable=1, >> delay=0, has_gpio=1 >> regulator_common_set_enable: done >> clock is enabled (380953Hz) >> Card did not respond to voltage select! >> gpio_request_tail: Node 'regulator-vcc_3v3', property 'gpio', failed >> to request GPIO index 0: -2 >> Regulator 'regulator-vcc_3v3' optional enable GPIO - not found! Error: -2 >> gpio_request_tail: Node 'regulator-flash_1v8', property 'gpio', failed >> to request GPIO index 0: -2 >> Regulator 'regulator-flash_1v8' optional enable GPIO - not found! Error: -2 >> clock is disabled (0Hz) >> regulator_common_set_enable: dev='regulator-vcc_3v3', enable=1, >> delay=0, has_gpio=0 >> clock is enabled (380953Hz) >> clock is enabled (25000000Hz) >> unable to select a mode >> switch to partitions #0, OK >> mmc1(part 0) is current device >> ** No partition table - mmc 1 ** >> MMC Device 2 not found >> no mmc device at slot 2 >> starting USB... >> Bus usb@ff500000: gpio_request_tail: Node 'regulator-vcc_5v', property >> 'gpio', failed to request GPIO index 0: -2 >> Regulator 'regulator-vcc_5v' optional enable GPIO - not found! Error: -2 >> regulator_common_set_enable: dev='regulator-usb_pwr_en', enable=1, >> delay=0, has_gpio=1 >> regulator_common_set_enable: done >> Register 3000140 NbrPorts 3 >> Starting the controller >> USB XHCI 1.10 >> scanning bus usb@ff500000 for devices... 1 USB Device(s) found >> scanning usb for storage devices... 0 Storage Device(s) found > > I have the same behavior with SEI610 on SM1, I need to check this fixes the issue... Could you try the following patches instead of this one ? https://patchwork.ozlabs.org/patch/1213648/ https://patchwork.ozlabs.org/patch/1213650/ Neil > > Neil > >> >> -Anand >> >
Hi Neil, + Jerome, On Sat, 21 Dec 2019 at 00:28, Anand Moon <linux.amoon@gmail.com> wrote: > > Hi Neil, > > > Could you try the following patches instead of this one ? > > > > https://patchwork.ozlabs.org/patch/1213648/ > > https://patchwork.ozlabs.org/patch/1213650/ > > > > Yes I have tried this series it worked for me. It's much better fix > than my approach. > Looks like I did some wrong testing, with microSD card connected, I missed that. For me at this point this issue persist. Here is the logs below. emmc switch 1 ok 00000000 emmc switch 2 ok fastboot data verify verify result: 255 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 00000000 emmc switch 0 ok Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from eMMC, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 bdlr_100_cur==435 aft test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 bdlr_100_cur==435 non-sec scramble use zero key ddr scramble enabled 100bdlr_step_size ps== 435 result report boot times 2Enable ddr reg access 00000000 emmc switch 3 ok Authentication key not yet programmed get rpmb counter error 0x00000007 00000000 emmc switch 0 ok Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x00088200, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz] OPS=0x40 ring efuse init chipver efuse init 29 0a 40 00 01 20 10 00 00 15 30 32 54 52 4d 50 [3.472682 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):ab8811b NOTICE: BL31: Built : 15:03:31, Feb 12 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2020.01-rc5-00009-g269c6e8c39 (Dec 20 2019 - 15:38:58 +0530) odroid-n2 Model: Hardkernel ODROID-N2 SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) DRAM: 3.8 GiB MMC: sd@ffe05000: 0, mmc@ffe07000: 1 In: serial@3000 Out: serial@3000 Err: serial@3000 Net: Warning: ethernet@ff3f0000 (eth0) using random MAC address - 4a:ab:15:ba:29:62 eth0: ethernet@ff3f0000 Hit any key to stop autoboot: 0 Card did not respond to voltage select! unable to select a mode switch to partitions #0, OK mmc1(part 0) is current device ** No partition table - mmc 1 ** MMC Device 2 not found no mmc device at slot 2 starting USB... Bus usb@ff500000: Register 3000140 NbrPorts 3 Starting the controller USB XHCI 1.10 scanning bus usb@ff500000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found complete logs in below linked. [0] http://pastebin.com/UsVMYAvW -Anand
Hi Neil, > Could you try the following patches instead of this one ? > > https://patchwork.ozlabs.org/patch/1213648/ > https://patchwork.ozlabs.org/patch/1213650/ > Yes I have tried this series it worked for me. It's much better fix than my approach. -Anand
On Fri 20 Dec 2019 at 19:47, Anand Moon <linux.amoon@gmail.com> wrote: > Hi Neil, + Jerome, > > On Sat, 21 Dec 2019 at 00:28, Anand Moon <linux.amoon@gmail.com> wrote: >> >> Hi Neil, >> >> > Could you try the following patches instead of this one ? >> > >> > https://patchwork.ozlabs.org/patch/1213648/ >> > https://patchwork.ozlabs.org/patch/1213650/ >> > >> >> Yes I have tried this series it worked for me. It's much better fix >> than my approach. >> > > Looks like I did some wrong testing, with microSD card connected, I missed that. > For me at this point this issue persist. Here is the logs below. > > emmc switch 1 ok > 00000000 > emmc switch 2 ok > fastboot data verify > verify result: 255 > Cfg max: 1, cur: 1. Board id: 255. Force loop cfg > DDR4 probe > ddr clk to 1320MHz > Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd0000, size: > 0x0000c000, part: 0 > 00000000 > emmc switch 0 ok > Check phy result > INFO : End of initialization > INFO : End of read enable training > INFO : End of fine write leveling > INFO : End of read dq deskew training > INFO : End of MPR read delay center optimization > INFO : End of Write leveling coarse delay > INFO : End of write delay center optimization > INFO : End of read delay center optimization > INFO : End of max read latency training > INFO : Training has run successfully! > 1D training succeed > Load ddrfw from eMMC, src: 0x00020200, des: 0xfffd0000, size: > 0x0000c000, part: 0 > Check phy result > INFO : End of initialization > INFO : End of 2D read delay Voltage center optimization > INFO : End of 2D write delay Voltage center optimization > INFO : Training has run successfully! > > R0_RxClkDly_Margin==82 ps 7 > R0_TxDqDly_Margi==106 ps 9 > > > R1_RxClkDly_Margin==0 ps 0 > R1_TxDqDly_Margi==0 ps 0 > > dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 > 2D training succeed > auto size-- 65535DDR cs0 size: 2048MB > DDR cs1 size: 2048MB > DMC_DDR_CTRL: 00600024DDR size: 3928MB > cs0 DataBus test pass > cs1 DataBus test pass > cs0 AddrBus test pass > cs1 AddrBus test pass > pre test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 > bdlr_100_cur==435 > aft test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 > bdlr_100_cur==435 > non-sec scramble use zero key > ddr scramble enabled > > 100bdlr_step_size ps== 435 > result report > boot times 2Enable ddr reg access > 00000000 > emmc switch 3 ok > Authentication key not yet programmed > get rpmb counter error 0x00000007 > 00000000 > emmc switch 0 ok > Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: > 0x00004000, part: 0 > Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x00088200, part: 0 > 0.0;M3 CHK:0;cm4_sp_mode 0 > E30HDR > MVN_1=0x00000000 > MVN_2=0x00000000 > [Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz] > OPS=0x40 > ring efuse init > chipver efuse init > 29 0a 40 00 01 20 10 00 00 15 30 32 54 52 4d 50 > [3.472682 Inits done] > secure task start! > high task start! > low task start! > run into bl31 > NOTICE: BL31: v1.3(release):ab8811b > NOTICE: BL31: Built : 15:03:31, Feb 12 2019 > NOTICE: BL31: G12A normal boot! > NOTICE: BL31: BL33 decompress pass > ERROR: Error initializing runtime service opteed_fast > > > U-Boot 2020.01-rc5-00009-g269c6e8c39 (Dec 20 2019 - 15:38:58 +0530) odroid-n2 > > Model: Hardkernel ODROID-N2 > SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) > DRAM: 3.8 GiB > MMC: sd@ffe05000: 0, mmc@ffe07000: 1 > In: serial@3000 > Out: serial@3000 > Err: serial@3000 > Net: > Warning: ethernet@ff3f0000 (eth0) using random MAC address - 4a:ab:15:ba:29:62 > eth0: ethernet@ff3f0000 > Hit any key to stop autoboot: 0 > Card did not respond to voltage select! > unable to select a mode > switch to partitions #0, OK > mmc1(part 0) is current device > ** No partition table - mmc 1 ** > MMC Device 2 not found > no mmc device at slot 2 > starting USB... > Bus usb@ff500000: Register 3000140 NbrPorts 3 > Starting the controller > USB XHCI 1.10 > scanning bus usb@ff500000 for devices... 1 USB Device(s) found > scanning usb for storage devices... 0 Storage Device(s) found > > complete logs in below linked. > [0] http://pastebin.com/UsVMYAvW > > -Anand I'm not quite sure I get what I should understand from this log. I can comment on the original patch though. I think you should keep the phase settings aligned with Linux. A) Among the exchange I had with amlogic, I got that there should always be a phase shift of 180 degree between the core and Tx phase. B) So far, Core=180, Tx=0, Rx=0 has proven to be quite stable for all the devices. I spent significant amount of time testing that. If that's not the case for the N2 under linux, please report it to the related ML. If these settings works under Linux, then it is not the problem and I don't think you should change them in u-boot.
Hi Jerome / Neil, [...] > > I'm not quite sure I get what I should understand from this log. > > I can comment on the original patch though. > > I think you should keep the phase settings aligned with Linux. > Thanks for this inputs. > A) Among the exchange I had with amlogic, I got that there should always > be a phase shift of 180 degree between the core and Tx phase. > > B) So far, Core=180, Tx=0, Rx=0 has proven to be quite stable for all > the devices. I spent significant amount of time testing that. > I feel you are referring below in mainline kernel #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ clk_reg = CLK_ALWAYS_ON(host); clk_reg |= CLK_DIV_MASK; clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); writel(clk_reg, host->regs + SD_EMMC_CLOCK); So in the current u-boot host we are not setting the correct bits for clock tuning I have modified with above changes and was able to boot into my Odorid N2 on emmc. I will check this out on my Odroid C2 and sdcard and then submit the next version. > If that's not the case for the N2 under linux, please report it to the > related ML. If these settings works under Linux, then it is not the > problem and I don't think you should change them in u-boot. ---- clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) switch to partitions #0, OK mmc2(part 0) is current device Scanning mmc 2:1... Found U-Boot script /boot/boot.scr 745 bytes read in 1 ms (727.5 KiB/s) ## Executing script at 08000000 27445760 bytes read in 605 ms (43.3 MiB/s) 65829 bytes read in 3 ms (20.9 MiB/s) 7404738 bytes read in 164 ms (43.1 MiB/s) ## Flattened Device Tree blob at 08008000 -Anand
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 031cc79ccb..87bea2888b 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc) meson_mmc_clk |= CLK_CO_PHASE_180; /* 180 phase tx clock */ - meson_mmc_clk |= CLK_TX_PHASE_000; + meson_mmc_clk |= CLK_TX_PHASE_180; /* clock settings */ meson_mmc_clk |= clk_src;
odroid n2 eMMC module would failed to boot up, because of TX phase clk failure, fix the typo in TX phase macro to help tune correct clk freqency. Before these changes. clock is enabled (380953Hz) clock is enabled (25000000Hz) after these changes clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) clock is enabled (52000000Hz) clock is enabled (52000000Hz) Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- Tested on new orange - eMMC AJNB4R 14.6 GiB MMC 5.1 old back - eMMC CGND3R 58.2 GiB MMC 5.0 --- drivers/mmc/meson_gx_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)