| Message ID | 20191122013659.2480-6-alexandru.marginean@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Joe Hershberger |
| Headers | show |
| Series | Introduce DSA Ethernet switch class and Felix driver | expand |
Am 2019-11-22 02:36, schrieb Alex Marginean: > The definition follows the DSA binding in kernel and describes the > switch, > its ports and PHYs. > ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028, it > is nitpicking.. LS1028A > not used in U-Boot and was disabled. it should be checked that the connected enetc port should be enabled. otherwise this driver goes awry. [snip]
Hi, sorry for the second mail. I've missed something. See below. Am 2019-11-22 02:36, schrieb Alex Marginean: > The definition follows the DSA binding in kernel and describes the > switch, > its ports and PHYs. > ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028, it > is > not used in U-Boot and was disabled. > > Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> > --- > arch/arm/dts/fsl-ls1028a-rdb.dts | 36 ++++++++++++++++++++++++++++ > arch/arm/dts/fsl-ls1028a.dtsi | 41 +++++++++++++++++++++++++++++++- > 2 files changed, 76 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts > b/arch/arm/dts/fsl-ls1028a-rdb.dts > index 3d5e8ade21..700fc067a4 100644 > --- a/arch/arm/dts/fsl-ls1028a-rdb.dts > +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts > @@ -114,9 +114,45 @@ > phy-handle = <&rdb_phy0>; > }; > > +ðsw_ports { > + port@0 { > + status = "okay"; > + phy-mode = "qsgmii"; > + phy-handle = <&sw_phy0>; > + }; > + port@1 { > + status = "okay"; > + phy-mode = "qsgmii"; > + phy-handle = <&sw_phy1>; > + }; > + port@2 { > + status = "okay"; > + phy-mode = "qsgmii"; > + phy-handle = <&sw_phy2>; > + }; > + port@3 { > + status = "okay"; > + phy-mode = "qsgmii"; > + phy-handle = <&sw_phy3>; > + }; > +}; > + > &mdio0 { > status = "okay"; > rdb_phy0: phy@2 { > reg = <2>; > }; > + > + sw_phy0: phy@10 { > + reg = <0x10>; > + }; > + sw_phy1: phy@11 { > + reg = <0x11>; > + }; > + sw_phy2: phy@12 { > + reg = <0x12>; > + }; > + sw_phy3: phy@13 { > + reg = <0x13>; > + }; > }; > diff --git a/arch/arm/dts/fsl-ls1028a.dtsi > b/arch/arm/dts/fsl-ls1028a.dtsi > index 43a154e8e7..a442fba4d0 100644 > --- a/arch/arm/dts/fsl-ls1028a.dtsi > +++ b/arch/arm/dts/fsl-ls1028a.dtsi > @@ -136,9 +136,48 @@ > reg = <0x000300 0 0 0 0>; > status = "disabled"; > }; > + ethsw: pci@0,5 { > + #address-cells=<0>; > + #size-cells=<1>; > + reg = <0x000500 0 0 0 0>; > + > + ethsw_ports: ports { #address-cells=<1>; #size-cells=<0>; > + port@0 { > + reg = <0>; > + status = "disabled"; > + label = "swp0"; > + }; > + port@1 { > + reg = <1>; > + status = "disabled"; > + label = "swp1"; > + }; > + port@2 { > + reg = <2>; > + status = "disabled"; > + label = "swp2"; > + }; > + port@3 { > + reg = <3>; > + status = "disabled"; > + label = "swp3"; > + }; > + port@4 { > + reg = <4>; > + phy-mode = "internal"; > + status = "okay"; > + ethernet = <&enetc2>; > + }; > + port@5 { > + reg = <5>; > + phy-mode = "internal"; > + status = "disabled"; > + }; > + }; > + }; > enetc6: pci@0,6 { > reg = <0x000600 0 0 0 0>; > - status = "okay"; > + status = "disabled"; > phy-mode = "internal"; > }; > };
Hi Michael, On 11/24/2019 1:11 AM, Michael Walle wrote: > Am 2019-11-22 02:36, schrieb Alex Marginean: >> The definition follows the DSA binding in kernel and describes the >> switch, >> its ports and PHYs. >> ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028, it is > > nitpicking.. LS1028A > > >> not used in U-Boot and was disabled. > > it should be checked that the connected enetc port should be enabled. > otherwise this driver goes awry. On LS1028A if mater Eth is disabled (ENETC PF2) there is a crash, I assume that's what you bumped into. From the looks of it that's caused by a hardware issue. For others reading this, the issue is making PCI PF5 (the switch) unable to use its internal MDIO registers if PF2 (master Eth) is disabled. I don't think I want to have switch driver code check on the ENETC functions, this should end up in a SoC erratum with the recommendation to have PF2 enabled when using the switch. On other platforms having a master Eth disabled means traffic through the switch won't work, but should not crash U-Boot either, uclass code seems to be fine in that regard. Thanks for the review and for the comments, I'll send a v2 for this series. Alex > > [snip] > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 3d5e8ade21..700fc067a4 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -114,9 +114,45 @@ phy-handle = <&rdb_phy0>; }; +ðsw_ports { + port@0 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy0>; + }; + port@1 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy1>; + }; + port@2 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy2>; + }; + port@3 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&sw_phy3>; + }; +}; + &mdio0 { status = "okay"; rdb_phy0: phy@2 { reg = <2>; }; + + sw_phy0: phy@10 { + reg = <0x10>; + }; + sw_phy1: phy@11 { + reg = <0x11>; + }; + sw_phy2: phy@12 { + reg = <0x12>; + }; + sw_phy3: phy@13 { + reg = <0x13>; + }; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 43a154e8e7..a442fba4d0 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -136,9 +136,48 @@ reg = <0x000300 0 0 0 0>; status = "disabled"; }; + ethsw: pci@0,5 { + #address-cells=<0>; + #size-cells=<1>; + reg = <0x000500 0 0 0 0>; + + ethsw_ports: ports { + port@0 { + reg = <0>; + status = "disabled"; + label = "swp0"; + }; + port@1 { + reg = <1>; + status = "disabled"; + label = "swp1"; + }; + port@2 { + reg = <2>; + status = "disabled"; + label = "swp2"; + }; + port@3 { + reg = <3>; + status = "disabled"; + label = "swp3"; + }; + port@4 { + reg = <4>; + phy-mode = "internal"; + status = "okay"; + ethernet = <&enetc2>; + }; + port@5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + }; + }; + }; enetc6: pci@0,6 { reg = <0x000600 0 0 0 0>; - status = "okay"; + status = "disabled"; phy-mode = "internal"; }; };
The definition follows the DSA binding in kernel and describes the switch, its ports and PHYs. ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028, it is not used in U-Boot and was disabled. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> --- arch/arm/dts/fsl-ls1028a-rdb.dts | 36 ++++++++++++++++++++++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 41 +++++++++++++++++++++++++++++++- 2 files changed, 76 insertions(+), 1 deletion(-)