| Message ID | 20191120213431.18111-2-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | 97a72bc28613733572b9632a51ab9c8680d45406 |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | [U-Boot,1/2] ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable | expand |
> -----Original Message----- > From: Marek Vasut <marex@denx.de> > Sent: Thursday, November 21, 2019 5:35 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; See, Chin Liang > <chin.liang.see@intel.com>; Dalon Westergreen <dwesterg@gmail.com>; > Dinh Nguyen <dinguyen@kernel.org>; Tan, Ley Foon > <ley.foon.tan@intel.com>; Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com> > Subject: [PATCH 2/2] ARM: socfpga: Purge pending transactions upon > enabling bridges on Gen5 > > On Gen5, when the FPGA is loaded and there was some prior interaction > between the HPS and the FPGA via bridges (e.g. Linux was running and using > some of the IPs in the FPGA) followed by warm reset, it has been observed > that there might be outstanding unfinished transactions. This leads to an > obscure misbehavior of the bridge. > > When the bridge is enabled again in U-Boot and there are outstanding > transactions, a read from within the bridge address range would return a > result of the previous read instead. Example: > => bridge enable ; md 0xff200000 1 > ff200000: 1234abcd > => bridge enable ; md 0xff200010 1 > ff200010: 5678dcba <------- this is in fact a value which is stored in > a memory at 0xff200000 => bridge enable ; md 0xff200000 1 > ff200000: 90effe09 <------- this is in fact a value which is stored in > a memory at 0xff200010 and so it continues. Issuing a write > does lock the system up completely. > > This patch opens the FPGA bridges in 'bridge enable' command, the tears > them down again, and then opens them again. This allows these outstanding > transactions to complete and makes this misbehavior go away. > > However, it is not entirely clear whether this is the correct solution. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Chin Liang See <chin.liang.see@intel.com> > Cc: Dalon Westergreen <dwesterg@gmail.com> > Cc: Dinh Nguyen <dinguyen@kernel.org> > Cc: Ley Foon Tan <ley.foon.tan@intel.com> > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Regards Ley Foon
On 11/21/19 10:59 AM, Tan, Ley Foon wrote: [...] Hi, >> Subject: [PATCH 2/2] ARM: socfpga: Purge pending transactions upon >> enabling bridges on Gen5 >> >> On Gen5, when the FPGA is loaded and there was some prior interaction >> between the HPS and the FPGA via bridges (e.g. Linux was running and using >> some of the IPs in the FPGA) followed by warm reset, it has been observed >> that there might be outstanding unfinished transactions. This leads to an >> obscure misbehavior of the bridge. >> >> When the bridge is enabled again in U-Boot and there are outstanding >> transactions, a read from within the bridge address range would return a >> result of the previous read instead. Example: >> => bridge enable ; md 0xff200000 1 >> ff200000: 1234abcd >> => bridge enable ; md 0xff200010 1 >> ff200010: 5678dcba <------- this is in fact a value which is stored in >> a memory at 0xff200000 => bridge enable ; md 0xff200000 1 >> ff200000: 90effe09 <------- this is in fact a value which is stored in >> a memory at 0xff200010 and so it continues. Issuing a write >> does lock the system up completely. >> >> This patch opens the FPGA bridges in 'bridge enable' command, the tears >> them down again, and then opens them again. This allows these outstanding >> transactions to complete and makes this misbehavior go away. >> >> However, it is not entirely clear whether this is the correct solution. >> >> Signed-off-by: Marek Vasut <marex@denx.de> >> Cc: Chin Liang See <chin.liang.see@intel.com> >> Cc: Dalon Westergreen <dwesterg@gmail.com> >> Cc: Dinh Nguyen <dinguyen@kernel.org> >> Cc: Ley Foon Tan <ley.foon.tan@intel.com> >> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> >> Cc: Tien Fong Chee <tien.fong.chee@intel.com> > > Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Do you think there is anyone still at Altera/intel who might be able to tell us what this problem really is about ? And whether there is some way to purge those stuck transactions without turning the bridges on and off and then on again ? Or whether there is a way to even verify there are stuck transactions ?
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 36f00aee31..65d3485bc5 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -228,6 +228,9 @@ void do_bridge_reset(int enable, unsigned int mask) writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); writel(iswgrp_handoff[1], &nic301_regs->remap); + + writel(0x7, &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst);
On Gen5, when the FPGA is loaded and there was some prior interaction between the HPS and the FPGA via bridges (e.g. Linux was running and using some of the IPs in the FPGA) followed by warm reset, it has been observed that there might be outstanding unfinished transactions. This leads to an obscure misbehavior of the bridge. When the bridge is enabled again in U-Boot and there are outstanding transactions, a read from within the bridge address range would return a result of the previous read instead. Example: => bridge enable ; md 0xff200000 1 ff200000: 1234abcd => bridge enable ; md 0xff200010 1 ff200010: 5678dcba <------- this is in fact a value which is stored in a memory at 0xff200000 => bridge enable ; md 0xff200000 1 ff200000: 90effe09 <------- this is in fact a value which is stored in a memory at 0xff200010 and so it continues. Issuing a write does lock the system up completely. This patch opens the FPGA bridges in 'bridge enable' command, the tears them down again, and then opens them again. This allows these outstanding transactions to complete and makes this misbehavior go away. However, it is not entirely clear whether this is the correct solution. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> --- arch/arm/mach-socfpga/misc_gen5.c | 3 +++ 1 file changed, 3 insertions(+)