[U-Boot,v2] armv8: layerscape: Manage PCIe EP compatible string via Kconfig
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Message ID 20191118135406.9697-1-pankaj.bansal@nxp.com
State Changes Requested
Delegated to: Priyanka Jain
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Series
  • [U-Boot,v2] armv8: layerscape: Manage PCIe EP compatible string via Kconfig
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Commit Message

Pankaj Bansal Nov. 18, 2019, 8:32 a.m. UTC
The ep node device tree name is governed by these bindings:
https://github.com/torvalds/linux/blob/master/Documentation/
devicetree/bindings/pci/layerscape-pci.txt#L24

As per above the ep compatible node contains platform name.
Therefore, define the ep node compatible as CONFIG to find the
pcie ep node in device tree during device tree fixup.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---

Notes:
    V2:
    - Modified the commit subject and body as per review comments

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 9 +++++++++
 drivers/pci/pcie_layerscape_fixup.c       | 4 ++--
 drivers/pci/pcie_layerscape_gen4_fixup.c  | 2 +-
 3 files changed, 12 insertions(+), 3 deletions(-)

Comments

Priyanka Jain Nov. 27, 2019, 6:33 a.m. UTC | #1
>-----Original Message-----
>From: Pankaj Bansal <pankaj.bansal@nxp.com>
>Sent: Monday, November 18, 2019 2:02 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; Xiaowei Bao
><xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
>Cc: u-boot@lists.denx.de; Pankaj Bansal <pankaj.bansal@nxp.com>
>Subject: [PATCH v2] armv8: layerscape: Manage PCIe EP compatible string via
>Kconfig
>
>The ep node device tree name is governed by these bindings:
>https://github.com/torvalds/linux/blob/master/Documentation/
>devicetree/bindings/pci/layerscape-pci.txt#L24
>
>As per above the ep compatible node contains platform name.
>Therefore, define the ep node compatible as CONFIG to find the pcie ep node
>in device tree during device tree fixup.
>
>Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
>---
>
>Notes:
>    V2:
>    - Modified the commit subject and body as per review comments
>
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 9 +++++++++
> drivers/pci/pcie_layerscape_fixup.c       | 4 ++--
> drivers/pci/pcie_layerscape_gen4_fixup.c  | 2 +-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
>diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>index bc3758f607..f8e7519994 100644
>--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>@@ -267,6 +267,15 @@ config FSL_PCIE_COMPAT
> 	  This compatible is used to find pci controller node in Kernel DT
> 	  to complete fixup.
>
>+config FSL_PCIE_EP_COMPAT
>+	string "PCIe EP compatible of Kernel DT"
>+	depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
>+	default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
>+	default "fsl,ls-pcie-ep"
>+	help
>+	  This compatible is used to find pci controller ep node in Kernel DT
>+	  to complete fixup.
>+
> config HAS_FEATURE_GIC64K_ALIGN
> 	bool
> 	default y if ARCH_LS1043A
>diff --git a/drivers/pci/pcie_layerscape_fixup.c
>b/drivers/pci/pcie_layerscape_fixup.c
>index 089e031724..194010f310 100644
>--- a/drivers/pci/pcie_layerscape_fixup.c
>+++ b/drivers/pci/pcie_layerscape_fixup.c
>@@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>- * Copyright 2017 NXP
>+ * Copyright 2017-2019 NXP
>  * Copyright 2014-2015 Freescale Semiconductor, Inc.
>  * Layerscape PCIe driver
>  */
>@@ -253,7 +253,7 @@ static void ft_pcie_ep_fix(void *blob, struct ls_pcie
>*pcie)  {
> 	int off;
>
>-	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
>+	off = fdt_node_offset_by_compat_reg(blob,
>CONFIG_FSL_PCIE_EP_COMPAT,
> 					    pcie->dbi_res.start);
> 	if (off < 0)
> 		return;
>diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c
>b/drivers/pci/pcie_layerscape_gen4_fixup.c
>index 1c9e5750bd..91e68eb84c 100644
>--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
>+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
>@@ -187,7 +187,7 @@ static void ft_pcie_ep_layerscape_gen4_fix(void *blob,
>struct ls_pcie_g4 *pcie)  {
> 	int off;
>
>-	off = fdt_node_offset_by_compat_reg(blob, "fsl,lx2160a-pcie-ep",
>+	off = fdt_node_offset_by_compat_reg(blob,
>CONFIG_FSL_PCIE_EP_COMPAT,
> 					    pcie->ccsr_res.start);
>
> 	if (off < 0) {
>--
>2.17.1
Break build for ls1021 based platforms . See
https://travis-ci.org/p-priyanka-jain/u-boot/jobs/617065004

Please ensure build for all platforms before sending next version

-priyankajain

Patch
diff mbox series

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index bc3758f607..f8e7519994 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -267,6 +267,15 @@  config FSL_PCIE_COMPAT
 	  This compatible is used to find pci controller node in Kernel DT
 	  to complete fixup.
 
+config FSL_PCIE_EP_COMPAT
+	string "PCIe EP compatible of Kernel DT"
+	depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+	default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
+	default "fsl,ls-pcie-ep"
+	help
+	  This compatible is used to find pci controller ep node in Kernel DT
+	  to complete fixup.
+
 config HAS_FEATURE_GIC64K_ALIGN
 	bool
 	default y if ARCH_LS1043A
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 089e031724..194010f310 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,6 +1,6 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
@@ -253,7 +253,7 @@  static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
 {
 	int off;
 
-	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
+	off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
 					    pcie->dbi_res.start);
 	if (off < 0)
 		return;
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
index 1c9e5750bd..91e68eb84c 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -187,7 +187,7 @@  static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
 {
 	int off;
 
-	off = fdt_node_offset_by_compat_reg(blob, "fsl,lx2160a-pcie-ep",
+	off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
 					    pcie->ccsr_res.start);
 
 	if (off < 0) {