Patchwork [U-Boot] Blackfin: define CONFIG_SYS_CACHELINE_SIZE

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Submitter Mike Frysinger
Date Oct. 13, 2011, 12:54 a.m.
Message ID <1318467293-5231-1-git-send-email-vapier@gentoo.org>
Download mbox | patch
Permalink /patch/119336/
State Accepted
Commit 8e5c1edadfe30656b380039ff58702a84cd738d1
Delegated to: Mike Frysinger
Headers show

Comments

Mike Frysinger - Oct. 13, 2011, 12:54 a.m.
Common U-Boot API wants this define, so import asm/cache.h from Linux
to provide suitable defines.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/include/asm/blackfin_local.h |    1 +
 arch/blackfin/include/asm/cache.h          |   70 ++++++++++++++++++++++++++++
 arch/blackfin/include/asm/config.h         |    3 +
 3 files changed, 74 insertions(+), 0 deletions(-)
 create mode 100644 arch/blackfin/include/asm/cache.h
Anton staaf - Oct. 13, 2011, 2:31 a.m.
On Wed, Oct 12, 2011 at 5:54 PM, Mike Frysinger <vapier@gentoo.org> wrote:
> Common U-Boot API wants this define, so import asm/cache.h from Linux
> to provide suitable defines.
>
> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
> ---
>  arch/blackfin/include/asm/blackfin_local.h |    1 +
>  arch/blackfin/include/asm/cache.h          |   70 ++++++++++++++++++++++++++++
>  arch/blackfin/include/asm/config.h         |    3 +
>  3 files changed, 74 insertions(+), 0 deletions(-)
>  create mode 100644 arch/blackfin/include/asm/cache.h
>
> diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
> index 27034d3..71207b6 100644
> --- a/arch/blackfin/include/asm/blackfin_local.h
> +++ b/arch/blackfin/include/asm/blackfin_local.h
> @@ -49,6 +49,7 @@
>  #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
>
>  #include <asm/linkage.h>
> +#include <asm/cache.h>
>
>  #ifndef __ASSEMBLY__
>  # ifdef SHARED_RESOURCES
> diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
> new file mode 100644
> index 0000000..482e4b5
> --- /dev/null
> +++ b/arch/blackfin/include/asm/cache.h
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright 2004-2009 Analog Devices Inc.
> + *
> + * Licensed under the GPL-2 or later.
> + */
> +
> +#ifndef __ARCH_BLACKFIN_CACHE_H
> +#define __ARCH_BLACKFIN_CACHE_H
> +
> +#include <asm/linkage.h>       /* for asmlinkage */
> +
> +/*
> + * Bytes per L1 cache line
> + * Blackfin loads 32 bytes for cache
> + */
> +#define L1_CACHE_SHIFT 5
> +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
> +#define SMP_CACHE_BYTES        L1_CACHE_BYTES
> +
> +#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
> +
> +#ifdef CONFIG_SMP
> +#define __cacheline_aligned
> +#else
> +#define ____cacheline_aligned
> +
> +/*
> + * Put cacheline_aliged data to L1 data memory
> + */
> +#ifdef CONFIG_CACHELINE_ALIGNED_L1
> +#define __cacheline_aligned                            \
> +         __attribute__((__aligned__(L1_CACHE_BYTES),   \
> +               __section__(".data_l1.cacheline_aligned")))
> +#endif
> +
> +#endif
> +
> +/*
> + * largest L1 which this arch supports
> + */
> +#define L1_CACHE_SHIFT_MAX     5
> +
> +#if defined(CONFIG_SMP) && \
> +    !defined(CONFIG_BFIN_CACHE_COHERENT)
> +# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
> +# define __ARCH_SYNC_CORE_ICACHE
> +# endif
> +# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
> +# define __ARCH_SYNC_CORE_DCACHE
> +# endif
> +#ifndef __ASSEMBLY__
> +asmlinkage void __raw_smp_mark_barrier_asm(void);
> +asmlinkage void __raw_smp_check_barrier_asm(void);
> +
> +static inline void smp_mark_barrier(void)
> +{
> +       __raw_smp_mark_barrier_asm();
> +}
> +static inline void smp_check_barrier(void)
> +{
> +       __raw_smp_check_barrier_asm();
> +}
> +
> +void resync_core_dcache(void);
> +void resync_core_icache(void);
> +#endif
> +#endif
> +
> +
> +#endif
> diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
> index 53af310..1a8de49 100644
> --- a/arch/blackfin/include/asm/config.h
> +++ b/arch/blackfin/include/asm/config.h
> @@ -21,6 +21,9 @@
>  # define CONFIG_BFIN_SCRATCH_REG retn
>  #endif
>
> +/* U-Boot wants this config name */
> +#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
> +
>  /* Make sure the structure is properly aligned */
>  #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
>  # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
> --
> 1.7.6.1
>
>

Acked-by: Anton Staaf <robotboy@chromium.org>

Patch

diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index 27034d3..71207b6 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -49,6 +49,7 @@ 
 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
 
 #include <asm/linkage.h>
+#include <asm/cache.h>
 
 #ifndef __ASSEMBLY__
 # ifdef SHARED_RESOURCES
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
new file mode 100644
index 0000000..482e4b5
--- /dev/null
+++ b/arch/blackfin/include/asm/cache.h
@@ -0,0 +1,70 @@ 
+/*
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ARCH_BLACKFIN_CACHE_H
+#define __ARCH_BLACKFIN_CACHE_H
+
+#include <asm/linkage.h>	/* for asmlinkage */
+
+/*
+ * Bytes per L1 cache line
+ * Blackfin loads 32 bytes for cache
+ */
+#define L1_CACHE_SHIFT	5
+#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
+#define SMP_CACHE_BYTES	L1_CACHE_BYTES
+
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
+#ifdef CONFIG_SMP
+#define __cacheline_aligned
+#else
+#define ____cacheline_aligned
+
+/*
+ * Put cacheline_aliged data to L1 data memory
+ */
+#ifdef CONFIG_CACHELINE_ALIGNED_L1
+#define __cacheline_aligned				\
+	  __attribute__((__aligned__(L1_CACHE_BYTES),	\
+		__section__(".data_l1.cacheline_aligned")))
+#endif
+
+#endif
+
+/*
+ * largest L1 which this arch supports
+ */
+#define L1_CACHE_SHIFT_MAX	5
+
+#if defined(CONFIG_SMP) && \
+    !defined(CONFIG_BFIN_CACHE_COHERENT)
+# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
+# define __ARCH_SYNC_CORE_ICACHE
+# endif
+# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
+# define __ARCH_SYNC_CORE_DCACHE
+# endif
+#ifndef __ASSEMBLY__
+asmlinkage void __raw_smp_mark_barrier_asm(void);
+asmlinkage void __raw_smp_check_barrier_asm(void);
+
+static inline void smp_mark_barrier(void)
+{
+	__raw_smp_mark_barrier_asm();
+}
+static inline void smp_check_barrier(void)
+{
+	__raw_smp_check_barrier_asm();
+}
+
+void resync_core_dcache(void);
+void resync_core_icache(void);
+#endif
+#endif
+
+
+#endif
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 53af310..1a8de49 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -21,6 +21,9 @@ 
 # define CONFIG_BFIN_SCRATCH_REG retn
 #endif
 
+/* U-Boot wants this config name */
+#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
+
 /* Make sure the structure is properly aligned */
 #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
 # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned