[U-Boot,05/12] net: gmac_rockchip: add support for px30
diff mbox series

Message ID 20191024232803.10338-6-heiko@sntech.de
State Accepted
Delegated to: Kever Yang
Headers show
Series
  • rockchip: add support for px30
Related show

Commit Message

Heiko Stuebner Oct. 24, 2019, 11:27 p.m. UTC
Add the glue code to allow the px30 variant of the Rockchip gmac
to provide network functionality.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 drivers/net/gmac_rockchip.c | 69 +++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

Comments

Kever Yang Oct. 25, 2019, 2:09 a.m. UTC | #1
On 2019/10/25 上午7:27, Heiko Stuebner wrote:
> Add the glue code to allow the px30 variant of the Rockchip gmac
> to provide network functionality.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Reviewed-by: Kever Yang<kever.yang@rock-chips.com>

Thanks,
- Kever

> ---
>   drivers/net/gmac_rockchip.c | 69 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 69 insertions(+)
>
> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
> index 26a6121175..3f3e38a2c6 100644
> --- a/drivers/net/gmac_rockchip.c
> +++ b/drivers/net/gmac_rockchip.c
> @@ -14,6 +14,7 @@
>   #include <asm/arch-rockchip/periph.h>
>   #include <asm/arch-rockchip/clock.h>
>   #include <asm/arch-rockchip/hardware.h>
> +#include <asm/arch-rockchip/grf_px30.h>
>   #include <asm/arch-rockchip/grf_rk322x.h>
>   #include <asm/arch-rockchip/grf_rk3288.h>
>   #include <asm/arch-rockchip/grf_rk3328.h>
> @@ -72,6 +73,47 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
>   	return designware_eth_ofdata_to_platdata(dev);
>   }
>   
> +static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
> +{
> +	struct px30_grf *grf;
> +	struct clk clk_speed;
> +	int speed, ret;
> +	enum {
> +		PX30_GMAC_SPEED_SHIFT = 0x2,
> +		PX30_GMAC_SPEED_MASK  = BIT(2),
> +		PX30_GMAC_SPEED_10M   = 0,
> +		PX30_GMAC_SPEED_100M  = BIT(2),
> +	};
> +
> +	ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
> +			      &clk_speed);
> +	if (ret)
> +		return ret;
> +
> +	switch (priv->phydev->speed) {
> +	case 10:
> +		speed = PX30_GMAC_SPEED_10M;
> +		ret = clk_set_rate(&clk_speed, 2500000);
> +		if (ret)
> +			return ret;
> +		break;
> +	case 100:
> +		speed = PX30_GMAC_SPEED_100M;
> +		ret = clk_set_rate(&clk_speed, 25000000);
> +		if (ret)
> +			return ret;
> +		break;
> +	default:
> +		debug("Unknown phy speed: %d\n", priv->phydev->speed);
> +		return -EINVAL;
> +	}
> +
> +	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
> +
> +	return 0;
> +}
> +
>   static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
>   {
>   	struct rk322x_grf *grf;
> @@ -257,6 +299,22 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
>   	return 0;
>   }
>   
> +static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
> +{
> +	struct px30_grf *grf;
> +	enum {
> +		PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
> +		PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
> +		PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
> +	};
> +
> +	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> +	rk_clrsetreg(&grf->mac_con1,
> +		     PX30_GMAC_PHY_INTF_SEL_MASK,
> +		     PX30_GMAC_PHY_INTF_SEL_RMII);
> +}
> +
>   static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
>   {
>   	struct rk322x_grf *grf;
> @@ -445,6 +503,10 @@ static int gmac_rockchip_probe(struct udevice *dev)
>   	ulong rate;
>   	int ret;
>   
> +	ret = clk_set_defaults(dev);
> +	if (ret)
> +		debug("%s clk_set_defaults failed %d\n", __func__, ret);
> +
>   	ret = clk_get_by_index(dev, 0, &clk);
>   	if (ret)
>   		return ret;
> @@ -569,6 +631,11 @@ const struct eth_ops gmac_rockchip_eth_ops = {
>   	.write_hwaddr		= designware_eth_write_hwaddr,
>   };
>   
> +const struct rk_gmac_ops px30_gmac_ops = {
> +	.fix_mac_speed = px30_gmac_fix_mac_speed,
> +	.set_to_rmii = px30_gmac_set_to_rmii,
> +};
> +
>   const struct rk_gmac_ops rk3228_gmac_ops = {
>   	.fix_mac_speed = rk3228_gmac_fix_mac_speed,
>   	.set_to_rgmii = rk3228_gmac_set_to_rgmii,
> @@ -600,6 +667,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
>   };
>   
>   static const struct udevice_id rockchip_gmac_ids[] = {
> +	{ .compatible = "rockchip,px30-gmac",
> +	  .data = (ulong)&px30_gmac_ops },
>   	{ .compatible = "rockchip,rk3228-gmac",
>   	  .data = (ulong)&rk3228_gmac_ops },
>   	{ .compatible = "rockchip,rk3288-gmac",

Patch
diff mbox series

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 26a6121175..3f3e38a2c6 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -14,6 +14,7 @@ 
 #include <asm/arch-rockchip/periph.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_px30.h>
 #include <asm/arch-rockchip/grf_rk322x.h>
 #include <asm/arch-rockchip/grf_rk3288.h>
 #include <asm/arch-rockchip/grf_rk3328.h>
@@ -72,6 +73,47 @@  static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
 	return designware_eth_ofdata_to_platdata(dev);
 }
 
+static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct px30_grf *grf;
+	struct clk clk_speed;
+	int speed, ret;
+	enum {
+		PX30_GMAC_SPEED_SHIFT = 0x2,
+		PX30_GMAC_SPEED_MASK  = BIT(2),
+		PX30_GMAC_SPEED_10M   = 0,
+		PX30_GMAC_SPEED_100M  = BIT(2),
+	};
+
+	ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed",
+			      &clk_speed);
+	if (ret)
+		return ret;
+
+	switch (priv->phydev->speed) {
+	case 10:
+		speed = PX30_GMAC_SPEED_10M;
+		ret = clk_set_rate(&clk_speed, 2500000);
+		if (ret)
+			return ret;
+		break;
+	case 100:
+		speed = PX30_GMAC_SPEED_100M;
+		ret = clk_set_rate(&clk_speed, 25000000);
+		if (ret)
+			return ret;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed);
+
+	return 0;
+}
+
 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk322x_grf *grf;
@@ -257,6 +299,22 @@  static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
 	return 0;
 }
 
+static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct px30_grf *grf;
+	enum {
+		PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
+		PX30_GMAC_PHY_INTF_SEL_MASK  = GENMASK(4, 6),
+		PX30_GMAC_PHY_INTF_SEL_RMII  = BIT(6),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	rk_clrsetreg(&grf->mac_con1,
+		     PX30_GMAC_PHY_INTF_SEL_MASK,
+		     PX30_GMAC_PHY_INTF_SEL_RMII);
+}
+
 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk322x_grf *grf;
@@ -445,6 +503,10 @@  static int gmac_rockchip_probe(struct udevice *dev)
 	ulong rate;
 	int ret;
 
+	ret = clk_set_defaults(dev);
+	if (ret)
+		debug("%s clk_set_defaults failed %d\n", __func__, ret);
+
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret)
 		return ret;
@@ -569,6 +631,11 @@  const struct eth_ops gmac_rockchip_eth_ops = {
 	.write_hwaddr		= designware_eth_write_hwaddr,
 };
 
+const struct rk_gmac_ops px30_gmac_ops = {
+	.fix_mac_speed = px30_gmac_fix_mac_speed,
+	.set_to_rmii = px30_gmac_set_to_rmii,
+};
+
 const struct rk_gmac_ops rk3228_gmac_ops = {
 	.fix_mac_speed = rk3228_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3228_gmac_set_to_rgmii,
@@ -600,6 +667,8 @@  const struct rk_gmac_ops rv1108_gmac_ops = {
 };
 
 static const struct udevice_id rockchip_gmac_ids[] = {
+	{ .compatible = "rockchip,px30-gmac",
+	  .data = (ulong)&px30_gmac_ops },
 	{ .compatible = "rockchip,rk3228-gmac",
 	  .data = (ulong)&rk3228_gmac_ops },
 	{ .compatible = "rockchip,rk3288-gmac",