[U-Boot,v3,3/6] arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
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Message ID 20191023080005.3273-4-vigneshr@ti.com
State Accepted
Commit 358032f9a5d76ecf64a52ad5fa189246fd82f834
Delegated to: Stefan Roese
Headers show
Series
  • J721e: Add HyperBus support
Related show

Commit Message

Vignesh Raghavendra Oct. 23, 2019, 8 a.m. UTC
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not
possible to use OSPI0 and HBMC simultaneously as they are muxed within
the Flash Subsystem hence disable HBMC by default as keep OSPI enabled.
Bootloader will fixup DT when it detects HyperFlash instead of OSPI.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---

v3:
Rebase onto latest master
Increase functional clock frequency to 250MHz
v2: No change

 arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Patch
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diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 01a8f4a9908f..14ffee584a88 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -118,4 +118,30 @@ 
 			loczrama = <1>;
 		};
 	};
+
+	fss: fss@47000000 {
+		compatible = "syscon", "simple-mfd";
+		reg = <0x0 0x47000000 0x0 0x100>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hbmc_mux: hbmc-mux {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4 0x2>; /* HBMC select */
+		};
+
+		hbmc: hyperbus@47034000 {
+			compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
+			reg = <0x0 0x47034000 0x0 0x100>,
+				<0x5 0x00000000 0x1 0x0000000>;
+			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			mux-controls = <&hbmc_mux 0>;
+			assigned-clocks = <&k3_clks 102 0>;
+			assigned-clock-rates = <250000000>;
+		};
+	};
 };