diff mbox series

[U-Boot] armv8: ls1028a: Updated lane C configuration to PCIe2 for 0x13BB

Message ID 20190904033459.1788-1-Zhiqiang.Hou@nxp.com
State Superseded
Delegated to: Prabhakar Kushwaha
Headers show
Series [U-Boot] armv8: ls1028a: Updated lane C configuration to PCIe2 for 0x13BB | expand

Commit Message

Z.Q. Hou Sept. 4, 2019, 3:33 a.m. UTC 
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

In SerDes protocol 0x13BB, lane C was erroneously asigned
to PCIe1, so fix it.

Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Priyanka Jain Sept. 16, 2019, 6:01 a.m. UTC | #1 
>From: Z.q. Hou
>Sent: Wednesday, September 4, 2019 9:03 AM
>To: u-boot@lists.denx.de; Prabhakar Kushwaha
><prabhakar.kushwaha@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
>Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
>Subject: [PATCH] armv8: ls1028a: Updated lane C configuration to PCIe2 for
>0x13BB
>
>From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
>In SerDes protocol 0x13BB, lane C was erroneously asigned to PCIe1, so fix it.
>
>Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support")
>Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Slight update in subject and description
Applied to fsl-qoriq master, awaiting upstream.

Thanks
priyankajain
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
index 5835a3a69e..313f3f1e8a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
@@ -24,7 +24,7 @@  static struct serdes_config serdes1_cfg_tbl[] = {
 	{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
 	{0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
 	{0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
-	{0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} },
+	{0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
 	{0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
 	{0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
 	{0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },