| Message ID | 20190723202758.21295-5-simon.k.r.goldschmidt@gmail.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | arm: socfpga: gen5: DM improvements | expand |
On 7/23/19 10:27 PM, Simon Goldschmidt wrote: > This moves disabling all peripherals from ad-hoc code in arch/arm > to the socfpga reset driver. That doesn't seem like what the patch does. Also, the WDT has to be kept enabled, is that functionality retained ? > To do this, DM initialization and UCLASS_RESET probing has to be done > earlier in the SPL. > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [...]
On Wed, Jul 24, 2019 at 9:31 AM Marek Vasut <marex@denx.de> wrote: > > On 7/23/19 10:27 PM, Simon Goldschmidt wrote: > > This moves disabling all peripherals from ad-hoc code in arch/arm > > to the socfpga reset driver. > > That doesn't seem like what the patch does. D'oh, you're right. I messed that up during development. In effect, this patch leaves periph reset like it was set by the boot rom. I'll have to work on v2 for that. Moving this code up is nevertheless required to have the reset driver available for the clock manager etc. Regards, Simon > > Also, the WDT has to be kept enabled, is that functionality retained ? > > > To do this, DM initialization and UCLASS_RESET probing has to be done > > earlier in the SPL. > > > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > [...]
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 9a32f5abfe..34e59b852b 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -48,19 +48,6 @@ void socfpga_per_reset(u32 reset, int set) clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); } -/* - * Assert reset on every peripheral but L4WD0. - * Watchdog must be kept intact to prevent glitches - * and/or hangs. - */ -void socfpga_per_reset_all(void) -{ - const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); - - writel(~l4wd0, &reset_manager_base->per_mod_reset); - writel(0xffffffff, &reset_manager_base->per2_mod_reset); -} - #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 87b76b47de..1ae8025746 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -84,12 +84,19 @@ void board_init_f(ulong dummy) socfpga_sdram_remap_zero(); socfpga_pl310_clear(); + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); - /* Put everything into reset but L4WD0. */ - socfpga_per_reset_all(); + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) + debug("Reset init failed: %d\n", ret); if (!socfpga_is_booting_from_fpga()) { /* Put FPGA bridges into reset too. */ @@ -130,16 +137,6 @@ void board_init_f(ulong dummy) debug_uart_init(); #endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_RESET, 0, &dev); - if (ret) - debug("Reset init failed: %d\n", ret); - /* enable console uart printing */ preloader_console_init();
This moves disabling all peripherals from ad-hoc code in arch/arm to the socfpga reset driver. To do this, DM initialization and UCLASS_RESET probing has to be done earlier in the SPL. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> --- arch/arm/mach-socfpga/reset_manager_gen5.c | 13 ------------- arch/arm/mach-socfpga/spl_gen5.c | 21 +++++++++------------ 2 files changed, 9 insertions(+), 25 deletions(-)