| Message ID | 1563448395-10564-1-git-send-email-Ashish.Kumar@nxp.com |
|---|---|
| State | Accepted |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | [U-Boot,v5] drivers: mtd: spi: Add micron mt35xu512a and mt35xu02g flash ID | expand |
On Thu, Jul 18, 2019 at 4:43 PM Ashish Kumar <Ashish.Kumar@nxp.com> wrote: > > mt35xu512a and mt35xu02g suports Single I/O and OCTAL I/O s/mt35xu512a/mt35xu512aba/ > also enable use of SPI_NOR_4B_OPCODES. > > These flashes are tested on LX2160ARDB and LS1028ARDB respectively > > Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> > Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> > --- > v5: > Is INFO inplace of INFO6 > v4: > Correct flash name to mt35xu512a in place of mt35xu512g > v3: > 1. Add version info, rebase to top > v2: > 1. Adding more description in commit msg. > 2. consolidating "http://patchwork.ozlabs.org/patch/1097867/" > and "http://patchwork.ozlabs.org/patch/1097867/" in single patch. > > drivers/mtd/spi/spi-nor-ids.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > index 2035fea..063cdeb 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -170,6 +170,8 @@ const struct flash_info spi_nor_ids[] = { > { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > + { INFO("mt35xu512a", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_4B_OPCODES) }, s/mt35xu512a/mt35xu512aba/ Applied to u-boot-spi/master
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2035fea..063cdeb 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -170,6 +170,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO("mt35xu512a", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_4B_OPCODES) }, + { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ /* Spansion/Cypress -- single (large) sector size only, at least