From a1f4984764c66c135cc385e6ea90ca24861bdcc4 Mon Sep 17 00:00:00 2001
From: kito <kito@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 18 Jul 2019 07:00:32 +0000
Subject: [PATCH] RISC-V: Fix splitter for 32-bit AND on 64-bit target.
Fixes github.com/riscv/riscv-gcc issue #161. We were accidentally using
BITS_PER_WORD to compute shift counts when we should have been using the
bitsize of the operand modes. This was wrong when we had an SImode shift
and a 64-bit target.
Andrew Waterman <andrew@sifive.com>
gcc/
* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
bitsize instead of BITS_PER_WORD.
gcc/testsuite/
* gcc.target/riscv/shift-shift-2.c: Add one more test.
gcc/ChangeLog:
2019-07-18 Kito Cheng <kito.cheng@sifive.com>
Backport from mainline
2019-07-08 Andrew Waterman <andrew@sifive.com>
Jim Wilson <jimw@sifive.com>
* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
bitsize instead of BITS_PER_WORD.
gcc/testsuite/
gcc/testsuite/ChangeLog:
2019-07-18 Kito Cheng <kito.cheng@sifive.com>
Backport from mainline
2019-07-08 Jim Wilson <jimw@sifive.com>
* gcc.target/riscv/shift-shift-2.c: Add one more test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@273566 138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 10 ++++++++++
gcc/config/riscv/riscv.md | 5 +++--
gcc/testsuite/ChangeLog | 7 +++++++
gcc/testsuite/gcc.target/riscv/shift-shift-2.c | 16 ++++++++++++++--
4 files changed, 34 insertions(+), 4 deletions(-)
@@ -1,3 +1,13 @@
+2019-07-18 Kito Cheng <kito.cheng@sifive.com>
+
+ Backport from mainline
+ 2019-07-08 Andrew Waterman <andrew@sifive.com>
+ Jim Wilson <jimw@sifive.com>
+
+ * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
+ bitsize instead of BITS_PER_WORD.
+ gcc/testsuite/
+
2019-07-17 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.c (pa_som_asm_init_sections): Don't force all constant
@@ -1775,10 +1775,11 @@
(set (match_dup 0)
(lshiftrt:GPR (match_dup 0) (match_dup 2)))]
{
- operands[2] = GEN_INT (BITS_PER_WORD
+ /* Op2 is a VOIDmode constant, so get the mode size from op1. */
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1]))
- exact_log2 (INTVAL (operands[2]) + 1));
})
-
+
;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros. This can be
;; split into two shifts. Otherwise it requires 3 instructions: li, sll, and.
(define_split
@@ -1,3 +1,10 @@
+2019-07-18 Kito Cheng <kito.cheng@sifive.com>
+
+ Backport from mainline
+ 2019-07-08 Jim Wilson <jimw@sifive.com>
+
+ * gcc.target/riscv/shift-shift-2.c: Add one more test.
+
2019-07-17 Andreas Krebbel <krebbel@linux.ibm.com>
Backport from mainline
@@ -25,5 +25,17 @@ sub4 (unsigned long i)
{
return (i << 52) >> 52;
}
-/* { dg-final { scan-assembler-times "slli" 4 } } */
-/* { dg-final { scan-assembler-times "srli" 4 } } */
+
+unsigned int
+sub5 (unsigned int i)
+{
+ unsigned int j;
+ j = i >> 24;
+ j = j * (1 << 24);
+ j = i - j;
+ return j;
+}
+/* { dg-final { scan-assembler-times "slli" 5 } } */
+/* { dg-final { scan-assembler-times "srli" 5 } } */
+/* { dg-final { scan-assembler-times "slliw" 1 } } */
+/* { dg-final { scan-assembler-times "srliw" 1 } } */
--
2.17.1