From patchwork Thu Jul 18 07:05:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 1133561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-505257-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="wCrWKZlI"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CLDMuA1C"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45q4sY3sBkz9s4Y for ; Thu, 18 Jul 2019 17:05:37 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=sSqyD7M7Ofo0Rez3Vny9rkOdesQnMeUZHmK5ruGp5gz0Of LNDNyVIWXfG4bdNWNHbm7R8aFV/J4Jqu9DboepeWFlPKg9ywvixbjsLxLSj45P1D 8BtMa+gn7oIOdfH6Yy13N3mGScz1idneVyPWPUe6jebm/zEN2RjQ49/bGfVTE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=ex03oh6ErnGIAkC75k3Fhaaz1is=; b=wCrWKZlI8Viu2OIriZm/ Pv6KY62fo2jPKwnE77hiC5I+qbRCSEHs150fdwF78XRm4L00PQMvcdb4ORgRarrp QJPMCF64OZ0z3EQW6eI3Vn+VNHBW1UVlj5R+lRLzLrwVfsAgLn+jmaaOeR8/kTUz eKnT736ytYe7cI4u6RezxG8= Received: (qmail 86463 invoked by alias); 18 Jul 2019 07:05:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 86454 invoked by uid 89); 18 Jul 2019 07:05:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=20190708 X-HELO: mail-wr1-f51.google.com Received: from mail-wr1-f51.google.com (HELO mail-wr1-f51.google.com) (209.85.221.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 18 Jul 2019 07:05:26 +0000 Received: by mail-wr1-f51.google.com with SMTP id p17so27357217wrf.11 for ; Thu, 18 Jul 2019 00:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=wfytFtUv8UlqzW47XKoPlCbHCytF8FUXwyE3eE4MIHM=; b=CLDMuA1CCm9Awp6LQ6hGeXFvHyLiDbH6UV2vDjWvJFqD9bWUBbVsCDltBdGo9FqPb7 c36ZY7BbrU//DL34BiR74y3trXGN0jXeqtycjZ9kjcpct3oZhHpC8LMBv9AQ70Ci2sQL wFMLa0Ddq39yH/YFyT+wnViXhC2qf7TPnMpojLIYxjQlk7ZeUJty+Q5TGvWxUvtabDb/ RZAmDCXxi1FKF0Mfw6PB7aMRj6FjkPsasJ4/q1VyAsS4kLlccqT7AZhtv0mc8dgu5fjI izCV8MtYf0kUNGXSBX8oge2ZJzI2/8rM07JO/P+aAkkfTT8PmRkUkAC5ZB/CdZTq8V33 HvkA== MIME-Version: 1.0 From: Kito Cheng Date: Thu, 18 Jul 2019 15:05:12 +0800 Message-ID: Subject: [COMMITTED][GCC9] Backport RISC-V: Fix splitter for 32-bit AND on 64-bit target. To: Jim Wilson , GCC Patches , kito.cheng@sifive.com X-IsSubscribed: yes Hi: I've backported this patch from trunk in order to fix a code gen error for RISC-V port. From a1f4984764c66c135cc385e6ea90ca24861bdcc4 Mon Sep 17 00:00:00 2001 From: kito Date: Thu, 18 Jul 2019 07:00:32 +0000 Subject: [PATCH] RISC-V: Fix splitter for 32-bit AND on 64-bit target. Fixes github.com/riscv/riscv-gcc issue #161. We were accidentally using BITS_PER_WORD to compute shift counts when we should have been using the bitsize of the operand modes. This was wrong when we had an SImode shift and a 64-bit target. Andrew Waterman gcc/ * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1] bitsize instead of BITS_PER_WORD. gcc/testsuite/ * gcc.target/riscv/shift-shift-2.c: Add one more test. gcc/ChangeLog: 2019-07-18 Kito Cheng Backport from mainline 2019-07-08 Andrew Waterman Jim Wilson * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1] bitsize instead of BITS_PER_WORD. gcc/testsuite/ gcc/testsuite/ChangeLog: 2019-07-18 Kito Cheng Backport from mainline 2019-07-08 Jim Wilson * gcc.target/riscv/shift-shift-2.c: Add one more test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@273566 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/riscv/riscv.md | 5 +++-- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/riscv/shift-shift-2.c | 16 ++++++++++++++-- 4 files changed, 34 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6c61632e373..22716b0c0c0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2019-07-18 Kito Cheng + + Backport from mainline + 2019-07-08 Andrew Waterman + Jim Wilson + + * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1] + bitsize instead of BITS_PER_WORD. + gcc/testsuite/ + 2019-07-17 John David Anglin * config/pa/pa.c (pa_som_asm_init_sections): Don't force all constant diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e3799a5bdd8..a8bac170e72 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1775,10 +1775,11 @@ (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] { - operands[2] = GEN_INT (BITS_PER_WORD + /* Op2 is a VOIDmode constant, so get the mode size from op1. */ + operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])) - exact_log2 (INTVAL (operands[2]) + 1)); }) - + ;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros. This can be ;; split into two shifts. Otherwise it requires 3 instructions: li, sll, and. (define_split diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ecd4b6a7178..de0b52ce248 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2019-07-18 Kito Cheng + + Backport from mainline + 2019-07-08 Jim Wilson + + * gcc.target/riscv/shift-shift-2.c: Add one more test. + 2019-07-17 Andreas Krebbel Backport from mainline diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c index 3f07e7776e7..10a5bb728be 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c @@ -25,5 +25,17 @@ sub4 (unsigned long i) { return (i << 52) >> 52; } -/* { dg-final { scan-assembler-times "slli" 4 } } */ -/* { dg-final { scan-assembler-times "srli" 4 } } */ + +unsigned int +sub5 (unsigned int i) +{ + unsigned int j; + j = i >> 24; + j = j * (1 << 24); + j = i - j; + return j; +} +/* { dg-final { scan-assembler-times "slli" 5 } } */ +/* { dg-final { scan-assembler-times "srli" 5 } } */ +/* { dg-final { scan-assembler-times "slliw" 1 } } */ +/* { dg-final { scan-assembler-times "srliw" 1 } } */ -- 2.17.1