[U-Boot,V3] drivers: mtd: spi: Add flash property for Micron mt25qu512a
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Message ID 1563344100-3931-1-git-send-email-Ashish.Kumar@nxp.com
State Accepted
Delegated to: Jagannadha Sutradharudu Teki
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  • [U-Boot,V3] drivers: mtd: spi: Add flash property for Micron mt25qu512a
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Commit Message

Ashish Kumar July 17, 2019, 6:15 a.m. UTC
mt25qu512a is rebranded after its spinoff from STM, so it is
different only in term of extended jedec ID, initial JEDEC id
is same as that of n25q512a.In order to avoid any confussion
with respect to name new entry is added.

This flash is tested for Single I/O mode on LS1046FRWY although
it also support QUAD I/O.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
v3:
1. Add version info, rebase to top
v2: 
2. Adding more description in commit msg

 drivers/mtd/spi/spi-nor-ids.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Jagan Teki July 18, 2019, 10:21 a.m. UTC | #1
On Wed, Jul 17, 2019 at 11:45 AM Ashish Kumar <Ashish.Kumar@nxp.com> wrote:
>
> mt25qu512a is rebranded after its spinoff from STM, so it is
> different only in term of extended jedec ID, initial JEDEC id
> is same as that of n25q512a.In order to avoid any confussion
> with respect to name new entry is added.
>
> This flash is tested for Single I/O mode on LS1046FRWY although
> it also support QUAD I/O.
>
> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> ---

Applied to u-boot-spi/master

Patch
diff mbox series

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index ec92976..d99c4c5 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -163,6 +163,8 @@  const struct flash_info spi_nor_ids[] = {
 	{ INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO6("mt25qu512a",  0x20bb20, 0x104400, 64 * 1024, 1024,
+		 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("n25q512a",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },