| Message ID | 20190213214659.22106-23-lukma@denx.de |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Stefano Babic |
| Headers | show |
| Series | imx: vybrid: Update BK4 and PCM052 boards to only use DM/DTS | expand |
On Wed, Feb 13, 2019 at 3:51 PM Lukasz Majewski <lukma@denx.de> wrote: > > BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices. > > Signed-off-by: Lukasz Majewski <lukma@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c > index 1e443a5850..c30df5df9d 100644 > --- a/board/phytec/pcm052/pcm052.c > +++ b/board/phytec/pcm052/pcm052.c > @@ -15,6 +15,7 @@ > #include <asm/arch/clock.h> > #include <led.h> > #include <environment.h> > +#include <miiphy.h> > > DECLARE_GLOBAL_DATA_PTR; > > @@ -382,6 +383,21 @@ int board_late_init(void) > > return 0; > } > + > +/** > + * KSZ8081 > + */ > +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f > +#define RMII_50MHz_CLOCK 0x8180 > + > +int board_phy_config(struct phy_device *phydev) > +{ > + /* Set 50 MHz reference clock */ > + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT, > + RMII_50MHz_CLOCK); Is it reasonable to use the clock infrastructure? Not necessarily instead of fixing this now, but would be a good direction. > + > + return genphy_config(phydev); > +} > #endif /* CONFIG_TARGET_BK4R1 */ > > int checkboard(void) > -- > 2.11.0 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot
Hi Joe, > On Wed, Feb 13, 2019 at 3:51 PM Lukasz Majewski <lukma@denx.de> wrote: > > > > BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY > > devices. > > > > Signed-off-by: Lukasz Majewski <lukma@denx.de> > > Acked-by: Joe Hershberger <joe.hershberger@ni.com> > > > --- > > > > Changes in v4: None > > Changes in v3: None > > Changes in v2: None > > > > board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/board/phytec/pcm052/pcm052.c > > b/board/phytec/pcm052/pcm052.c index 1e443a5850..c30df5df9d 100644 > > --- a/board/phytec/pcm052/pcm052.c > > +++ b/board/phytec/pcm052/pcm052.c > > @@ -15,6 +15,7 @@ > > #include <asm/arch/clock.h> > > #include <led.h> > > #include <environment.h> > > +#include <miiphy.h> > > > > DECLARE_GLOBAL_DATA_PTR; > > > > @@ -382,6 +383,21 @@ int board_late_init(void) > > > > return 0; > > } > > + > > +/** > > + * KSZ8081 > > + */ > > +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f > > +#define RMII_50MHz_CLOCK 0x8180 > > + > > +int board_phy_config(struct phy_device *phydev) > > +{ > > + /* Set 50 MHz reference clock */ > > + phy_write(phydev, MDIO_DEVAD_NONE, > > MII_KSZ8081_REFERENCE_CLOCK_SELECT, > > + RMII_50MHz_CLOCK); > > Is it reasonable to use the clock infrastructure? Yes, I do have in the back of my head that this shall be done via clock API. However, it is a long way to and I would like first to have the DM/DTS cleanup patches in main line. > Not necessarily > instead of fixing this now, but would be a good direction. > > > + > > + return genphy_config(phydev); > > +} > > #endif /* CONFIG_TARGET_BK4R1 */ > > > > int checkboard(void) > > -- > > 2.11.0 > > > > _______________________________________________ > > U-Boot mailing list > > U-Boot@lists.denx.de > > https://lists.denx.de/listinfo/u-boot Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 1e443a5850..c30df5df9d 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -15,6 +15,7 @@ #include <asm/arch/clock.h> #include <led.h> #include <environment.h> +#include <miiphy.h> DECLARE_GLOBAL_DATA_PTR; @@ -382,6 +383,21 @@ int board_late_init(void) return 0; } + +/** + * KSZ8081 + */ +#define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f +#define RMII_50MHz_CLOCK 0x8180 + +int board_phy_config(struct phy_device *phydev) +{ + /* Set 50 MHz reference clock */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT, + RMII_50MHz_CLOCK); + + return genphy_config(phydev); +} #endif /* CONFIG_TARGET_BK4R1 */ int checkboard(void)
BK4 requires setup of 50MHz reference clock for its KSZ8081 PHY devices. Signed-off-by: Lukasz Majewski <lukma@denx.de> --- Changes in v4: None Changes in v3: None Changes in v2: None board/phytec/pcm052/pcm052.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)